Add tests for CHIRRTL mem port definitions.

Including using different clocks and ports defined in when scope.

3 files changed, 113 insertions, 1 deletions

diff --git a/src/test/resources/features/CHIRRTLMems.fir b/src/test/resources/features/CHIRRTLMems.fir
new file mode 100644
index 00000000..bd92c872
--- /dev/null
+++ b/src/test/resources/features/CHIRRTLMems.fir
@@ -0,0 +1,34 @@
+
+circuit ChirrtlMems :
+  module ChirrtlMems :
+    input clk : Clock
+    input reset : UInt<1>
+
+    cmem ram : UInt<32>[16]
+    node newClock = clk
+
+    wire wen : UInt<1>
+    wen <= not(reset) ; Don't const prop me!
+
+    reg raddr : UInt<4>, clk with : (reset => (reset, UInt(0)))
+    raddr <= add(raddr, UInt(1))
+    infer mport r = ram[raddr], newClock
+
+    when wen :
+      node newerClock = clk
+      reg waddr : UInt<4>, clk with : (reset => (reset, UInt(0)))
+      waddr <= add(waddr, UInt(1))
+      infer mport w = ram[waddr], newerClock
+      w <= waddr
+
+      when eq(waddr, UInt(0)) :
+        raddr <= UInt(0)
+
+    when not(reset) :
+      when gt(waddr, UInt(1)) :
+        when neq(r, raddr) :
+          printf(clk, UInt(1), "Assertion failed! r =/= raddr\n")
+          stop(clk, UInt(1), 1) ; Failure!
+      when eq(raddr, UInt(15)) :
+        stop(clk, UInt(1), 0) ; Success!
+    
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
new file mode 100644
index 00000000..dd2b7e31
--- /dev/null
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -0,0 +1,78 @@
+/*
+Copyright (c) 2014 - 2016 The Regents of the University of
+California (Regents). All Rights Reserved.  Redistribution and use in
+source and binary forms, with or without modification, are permitted
+provided that the following conditions are met:
+   * Redistributions of source code must retain the above
+     copyright notice, this list of conditions and the following
+     two paragraphs of disclaimer.
+   * Redistributions in binary form must reproduce the above
+     copyright notice, this list of conditions and the following
+     two paragraphs of disclaimer in the documentation and/or other materials
+     provided with the distribution.
+   * Neither the name of the Regents nor the names of its contributors
+     may be used to endorse or promote products derived from this
+     software without specific prior written permission.
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
+ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF
+ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION
+TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+MODIFICATIONS.
+*/
+
+package firrtlTests
+
+import java.io._
+import org.scalatest._
+import org.scalatest.prop._
+import firrtl.{Parser,Circuit}
+import firrtl.passes._
+
+class ChirrtlSpec extends FirrtlFlatSpec {
+
+  "Chirrtl memories" should "allow ports with clocks defined after the memory" in {
+    val passes = Seq(
+      CInferTypes,
+      CInferMDir,
+      RemoveCHIRRTL,
+      ToWorkingIR,            
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      ResolveGenders,
+      CheckGenders,
+      InferWidths,
+      CheckWidths,
+      PullMuxes,
+      ExpandConnects,
+      RemoveAccesses,
+      ExpandWhens,
+      CheckInitialization
+    )
+    val input =
+     """circuit Unit :
+       |  module Unit :
+       |    input clk : Clock
+       |    smem ram : UInt<32>[128]
+       |    node newClock = clk
+       |    infer mport x = ram[UInt(2)], newClock
+       |    x <= UInt(3)
+       |    when UInt(1) :
+       |      infer mport y = ram[UInt(4)], newClock
+       |      y <= UInt(5)
+       """.stripMargin
+    passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+  }
+
+  it should "compile and run" in {
+    runFirrtlTest("CHIRRTLMems", "/features")
+  }
+}
diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala
index 0793cb8a..930100b3 100644
--- a/src/test/scala/firrtlTests/FirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/FirrtlSpec.scala
@@ -148,5 +148,5 @@ trait FirrtlRunners extends BackendCompilationUtilities {
 
 class FirrtlPropSpec extends PropSpec with PropertyChecks with FirrtlRunners
 
-class FirrtlFlatSpec extends FlatSpec with Matchers
+class FirrtlFlatSpec extends FlatSpec with Matchers with FirrtlRunners