Change RemoveCHIRRTL to define port clocks at CHIRRTL port definition

Invalidate clock at mem definition. Fixes #131

2 files changed, 9 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 59aee8c4..ceccccbc 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -77,6 +77,7 @@ class VerilogEmitter extends Emitter {
          (tpe(e)) match {
             case (t:UIntType) => e
             case (t:SIntType) => Seq("$signed(",e,")")
+            case (t:ClockType) => e
          }
       }
       (x) match {
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index ccc02f24..18ad7e16 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -1764,7 +1764,7 @@ object RemoveCHIRRTL extends Pass {
                   def set_poison (vec:Seq[MPort],addr:String) : Unit = {
                      for (r <- vec ) {
                         stmts += IsInvalid(s.info,SubField(SubField(Ref(s.name,ut),r.name,ut),addr,taddr))
-                        stmts += Connect(s.info,SubField(SubField(Ref(s.name,ut),r.name,ut),"clk",taddr),r.clk)
+                        stmts += IsInvalid(s.info,SubField(SubField(Ref(s.name,ut),r.name,ut),"clk",taddr))
                      }
                   }
                   def set_enable (vec:Seq[MPort],en:String) : Unit = {
@@ -1801,24 +1801,28 @@ object RemoveCHIRRTL extends Pass {
                case (s:CDefMPort) => {
                   mport_types(s.name) = mport_types(s.mem)
                   val addrs = ArrayBuffer[String]()
+                  val clks = ArrayBuffer[String]()
                   val ens = ArrayBuffer[String]()
                   val masks = ArrayBuffer[String]()
                   s.direction match {
                      case MReadWrite => {
                         repl(s.name) = DataRef(SubField(Ref(s.mem,ut),s.name,ut),"rdata","data","mask",true)
                         addrs += "addr"
+                        clks += "clk"
                         ens += "en"
                         masks += "mask"
                      }
                      case MWrite => {
                         repl(s.name) = DataRef(SubField(Ref(s.mem,ut),s.name,ut),"data","data","mask",false)
                         addrs += "addr"
+                        clks += "clk"
                         ens += "en"
                         masks += "mask"
                      }
                      case _ => {
                         repl(s.name) = DataRef(SubField(Ref(s.mem,ut),s.name,ut),"data","data","blah",false)
                         addrs += "addr"
+                        clks += "clk"
                         ens += "en"
                      }
                   }
@@ -1826,6 +1830,9 @@ object RemoveCHIRRTL extends Pass {
                   for (x <- addrs ) {
                      stmts += Connect(s.info,SubField(SubField(Ref(s.mem,ut),s.name,ut),x,ut),s.exps(0))
                   }
+                  for (x <- clks ) {
+                     stmts += Connect(s.info,SubField(SubField(Ref(s.mem,ut),s.name,ut),x,ut),s.exps(1))
+                  }
                   for (x <- ens ) {
                      stmts += Connect(s.info,SubField(SubField(Ref(s.mem,ut),s.name,ut),x,ut),one)
                   }