Add HasInfo trait to IR, IsDeclaration mixes in HasInfo

Change Field from IsDeclaration to HasName

Make WDefInstance an IsDeclaration

2 files changed, 13 insertions, 10 deletions

diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index 7d4a9f5c..66a00229 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -51,7 +51,10 @@ trait AST {
 trait HasName {
   val name: String
 }
-trait IsDeclaration extends HasName
+trait HasInfo {
+  val info: Info
+}
+trait IsDeclaration extends HasName with HasInfo
 
 case class StringLit(array: Array[Byte]) extends AST
 
@@ -114,13 +117,13 @@ case class DefInstance(info: Info, name: String, module: String) extends Stmt wi
 case class DefMemory(info: Info, name: String, data_type: Type, depth: Int, write_latency: Int, 
                read_latency: Int, readers: Seq[String], writers: Seq[String], readwriters: Seq[String]) extends Stmt with IsDeclaration
 case class DefNode(info: Info, name: String, value: Expression) extends Stmt with IsDeclaration
-case class Conditionally(info: Info, pred: Expression, conseq: Stmt, alt: Stmt) extends Stmt
+case class Conditionally(info: Info, pred: Expression, conseq: Stmt, alt: Stmt) extends Stmt with HasInfo
 case class Begin(stmts: Seq[Stmt]) extends Stmt
-case class BulkConnect(info: Info, loc: Expression, exp: Expression) extends Stmt
-case class Connect(info: Info, loc: Expression, exp: Expression) extends Stmt
-case class IsInvalid(info: Info, exp: Expression) extends Stmt
-case class Stop(info: Info, ret: Int, clk: Expression, en: Expression) extends Stmt
-case class Print(info: Info, string: StringLit, args: Seq[Expression], clk: Expression, en: Expression) extends Stmt
+case class BulkConnect(info: Info, loc: Expression, exp: Expression) extends Stmt with HasInfo
+case class Connect(info: Info, loc: Expression, exp: Expression) extends Stmt with HasInfo
+case class IsInvalid(info: Info, exp: Expression) extends Stmt with HasInfo
+case class Stop(info: Info, ret: Int, clk: Expression, en: Expression) extends Stmt with HasInfo
+case class Print(info: Info, string: StringLit, args: Seq[Expression], clk: Expression, en: Expression) extends Stmt with HasInfo
 case class Empty() extends Stmt
 
 trait Width extends AST {
@@ -148,7 +151,7 @@ trait Flip extends AST
 case object DEFAULT extends Flip
 case object REVERSE extends Flip
 
-case class Field(name: String, flip: Flip, tpe: Type) extends AST with IsDeclaration // ?
+case class Field(name: String, flip: Flip, tpe: Type) extends AST with HasName
 
 trait Type extends AST
 case class UIntType(width: Width) extends Type
@@ -172,5 +175,5 @@ trait Module extends AST with IsDeclaration {
 case class InModule(info: Info, name: String, ports: Seq[Port], body: Stmt) extends Module
 case class ExModule(info: Info, name: String, ports: Seq[Port]) extends Module
 
-case class Circuit(info: Info, modules: Seq[Module], main: String) extends AST
+case class Circuit(info: Info, modules: Seq[Module], main: String) extends AST with HasInfo
 
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index 74ccabf4..7360a77b 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -55,7 +55,7 @@ case class WSubIndex(exp:Expression,value:Int,tpe:Type,gender:Gender) extends Ex
 case class WSubAccess(exp:Expression,index:Expression,tpe:Type,gender:Gender) extends Expression
 case class WVoid() extends Expression { def tpe = UnknownType() }
 case class WInvalid() extends Expression { def tpe = UnknownType() }
-case class WDefInstance(info:Info,name:String,module:String,tpe:Type) extends Stmt 
+case class WDefInstance(info:Info,name:String,module:String,tpe:Type) extends Stmt with IsDeclaration
 
 case object ADDW_OP extends PrimOp 
 case object SUBW_OP extends PrimOp