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* InstanceKeyGraph: add staticInstanceCount, getGraph and getChildrenInstanceMap
* InstanceKeyGraph: reachableModules, unreachableModules, lowestCommonAncestor and fullHierarchy
* Replace usage of InstanceGraph with InstanceKeyGraph
Also deprecates all unused methods.
* WiringUtils: make new version of sinksToSources package private
This will make our live easier next time we need to change it.
* CircuitGraph: use InstanceKeyGraph
* InstanceKeyGraphSpec: respect maximum line width
* InstanceKeyGraph: make constructor private
* InstanceKeyGraph: move lowestCommonAncestor function to Wiring
* WiringUtils: update deprecation message
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* Use signed output in LargeParamExecutionTest
Change the Verilog used in LargeParamExecutionTest to match its
ExtModule specification. An ExtModule with an SInt port should map to
a separate Verilog module with a signed port and this is disjoint from
an ExtModule with a UInt port.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Error on ExtModules w/ same defname, diff. ports
Adds a high form check to ensure that external modules that have the
same defname also have exactly the same ports.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Avoid repeated inlining in FlattenRegUpdate
When-else structure can lead to the same complex mux structure being
the default on several branches in register update logic. When these are
inlined, it can lead to artifical unreachable branches that show up as
coverage holes in coverage of the emitted Verilog. This commit changes
the inlining logic to prevent inlining any reference expression that
shows up multiple times because this is a common indicator of the
problematic case.
* Add tests for improved register update logic emission
* Improve FlattenRegUpdate comment and add more tests
* [skip formal checks] ICache equivalence check verified locally
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* WIP Commit
* Add EdgeDataDiGraph with views to amortize graph construction
* WIP, got basic structure, need tests to pipeclean
* First tests pass. Need more.
* Tests pass, more need to be written
* More tests pass! Things should work, except for memories
* Added clearPrev to fix digraph uses where caching prev breaks
* Removed old Component. Documented IRLookup
* Added comments. Make prev arg to getEdges
* WIP: Refactoring for CircuitGraph
* Refactored into CircuitGraph. Can do topological module analysis
* Removed old versions
* Added support for memories
* Added cached test
* More stufffff
* Added implicit caching of connectivity
* Added tests for IRLookup, and others
* Many major changes.
Replaced CircuitGraph as ConnectionGraph
Added CircuitGraph to be top-level user-facing object
ConnectionGraph now automatically shortcuts getEdges
ConnectionGraph overwrites BFS as PriorityBFS
Added leafModule to Target
Added lookup by kind to IRLookup
Added more tests
* Reordered stuff in ConnectionGraph
* Made path work with deep hierarchies. Added PML for IllegalClockCrossings
* Made pathsInDAG work with current shortcut semantics
* Bugfix: check pathless targets when shortcutting paths
* Added documentation/licenses
* Removed UnnamedToken and related functionality
* Added documentation of ConnectionGraph
* Added back topo, needed for correct solving of intermediate modules
* Bugfix. Cache intermediate clockSources from same BFS with same root, but not BFS with different root
* Added literal/invalid clock source, and unknown top for getclocksource
* Bugfix for clocks in bundles
* Add CompleteTargetSerializer and test
* remove ClockFinder, be able to compile.
* test is able to compile, but need to fix.
* public and abstract DiGraph, remove DiGraphLike.
* revert some DiGraph code, ConnectionGraphSpec passed.
* CircuitGraphSpec passed.
* minimize diff between master
* codes clean up
* override linearize and revert DiGraph
* keep DiGraph unchanged.
* make ci happy again.
* codes clean up.
* bug fix for rebase
* remove wir
* make scaladoc happy again.
* update for review.
* add some documentation.
* remove tag
* wip IRLookup
* code clean up and add some doucmentations.
* IRLookup cache with ModuleTarget guarded.
* make unidoc and 2.13 happy
Co-authored-by: Adam Izraelevitz <azidar@gmail.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* ir: use Serializer.serialize where possible
* ir.Serializer: serialize MultiInfo correctly
* ir.Serializer: empty body needs to result in a skip statement
The firrtl grammar requires at least one statement.
* ir.Serializer: correctly serialize fixed point types and literals
* Serializer: change Seq -> Iterable in order to be Scala 2.13 compatible
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The values end up being converted to BigDecimal
anyways.
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* WiringUtils.sinksToSources: make sinkInsts order deterministic
* WiringUtils: make owners a LinkedHashMap
* Wiring: only make something a Wire if it isn't a port already
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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invalidation (#1797)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* InferTypesFlowsAndKindsSpec: test the results of InferTypes, ResolveKinds and ResolveFlows
* Don't use passes sub-package in tests
This changes two test files using the "passes" sub-package to
"firrtl.passes". This allows a new "firrtlTests.passes" package to be
freely created and used without a name collision.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* ResolveFlows: only depends on types and working ir
The types are needed to know the orientation of
a bundle field of a SubField node.
* InferTypes: fix bugs with unknown widths on ports and memories
* LoweringCompileSpec: Uniquify pass moved
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* RenameMapSpec: try rename instance and port
* RenameMapSpec: explicit chaining is required
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add specific test for shadowing
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Move new transforms, recently added, into existing or new sets of
transforms (defined in firrtl.stage.Forms).
One transform is a mandatory low FIRRTL optimization:
- firrtl.transforms.LegalizeAndReductionsTransform
Previously, this was included as a prerequisite of all Verilog
emitters (minimum, normal, and SystemVerilog).
Two transforms associated with converting and removing the new
verification statements are moved into a new set of transforms,
AssertsRemoved:
- firrtl.transforms.formal.ConvertAsserts
- firrtl.transforms.formal.RemoveVerificationStatements
Previously, these transforms were directly added as prerequisites to
the minimum Verilog and normal Verilog emitter, but not the
SystemVerilog emitter.
The designation of inputForm=LowForm for legacy, custom transforms is
updated to include assertion removal transforms as part of their
optionalPrerequisites. This has the effect of continuing to cause
inputForm=LowForm transforms to run as late as possible (right before
the low FIRRTL, minimum Verilog, Verilog, or SystemVeriog emitter).
Tests are updated to reflect the new order in both CustomTransformSpec
and LoweringCompilersSpec.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add sign-extend const-prop test
* Emitter: don't wrap Neg operand in concat
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* add const prop bitwise reduction equivalence test
* mask negative literals when propagating reduction
* change widths
* get rid of unnecessary if
* add BigInt mask utility
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* ConstProp: test bitwise op of signed literals
* ConstProp: use bit mask for FoldOr/FoldXor
* handle and also
* add UIntLiteral.masked helper
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* test const prop of addition of negative literals
* Emitter: handle minimum negative values correctly
* update expected verilog in AsyncResetSpec
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* dedup: add faster InstanceGraph implementation and use it in dedup
The new implementation takes care not to hash the instance
types contained in DefInstance nodes.
This should make dedup considerably faster.
* FastInstanceGraph: cache vertices for faster findInstancesInHierarchy
* FastInstanceGraph: remove the parent name field since it isn't actually necessary
* FastInstanceGraph -> InstanceKeyGraph
* InstanceGraph: describe performance problems.
* InstanceKeyGraph: turn moduleMap into a def instead of a val
This will make changing implementation details much easier
in the future.
* InstanceKeyGraph: return childInstances as Seq instead of Map
This ensures a deterministic iteration order and it
can easily be turned into a Map for O(1) accesses.
* InstanceKeyGraph: add tests for public methods
* InstanceKeyGraph: group public methods together
* InstanceKeyGraphSpec: fix wording of a comment
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* [WIP] Propagate source locators to Verilog if-else emission
* Add and fix tests for reg update info propagation
* Add limited source locator propagation in ConstProp
Support propagating source locators on connections or nodes where the
right-hand side is simply a reference. This case comes up a lot for
registers without a synchronous reset.
node _T_1 = x @[MyFile.scala 12:10]
node _T_2 = _T_1
z <= x
Previousy the source locator would be lost, now the result is:
z <= x @[MyFile.scala 12:10]
* Address review comments
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Refactor the test used in the CustomTransformSpec to assert that
inputForm=LowForm legacy transforms run right before the emitter (see
note below!). The new test looks only for a list of (customTransform,
emitter) in a sliding, size-2 window of the flattened transform order.
Previously, this was looking for a match before and after the custom
transform. The old implementation necessitate busywork updates of the
test when new transforms are added that changed the transform running
before the custom transform.
Note: this test, as written is intentionally wrong. When verification
statements were added, the test was changed to not do what it's
supposed to do. Namely, the test is supposed to ensure that an
inputForm=LowForm transform runs immediately before its emitter.
However, the test is actually checking that the custom transform runs
before transforms that convert and remove verification statements. I'm
intentionally leaving the test broken, but doing the refactor in order
to make this easier to manually backport to the 1.3.x branch.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Remove tests from LoweringCompilerSpec testing the placement of
inputForm=LowForm legacy, custom transforms. This behavior is already
tested in the CustomTransformSpec.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This should speed up the common case
as the compiler never operates on the
unescaped string.
The new escape function also fixes a bug
where ']' was not escaped even though it
is the delimiting character for FileInfo.
In order to maintain backwards
compatibility for the ProtoBuf format,
this patch adds escape/unescape calls
when going from/to protobuf format.
For better performance we should consider
changing the protobuf format.
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For multi-line registers, the parsed source locator is located in a
different place in the concrete syntax tree than it is for other
Statements.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* benchmark: add hot.DedupBenchmark
* dedup: use structural md5 hash instead of agnostify and serialize
* StructuralHash: generate PrimOp LUT
* StructuralHash: change MessageDigestHasher to not be a case class
* StructuralHash: we want Blocks and EmptyStmt to be ignored
* StructuralHash: use SHA-256 instead of MD5
* StructuralHash: clarify extmodule port name agnistification
* StructuralHash: hash the name of width vars instead of trying to agnostify
This should be in line with the old Dedup behavior.
The prior use of n(..) was incorrect since the namespace
of these vars is different from the normal module scope namespace.
* StructuralHash: address Schuyler's review comments
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This Serializer which is implemented
external to the IR node definition
uses a StringBuilder to achieve about a
1.7x performance improvement when serializing.
Eventually, all implementations of the
`serialize` methd should be replaced with
a call to `Serializer.serialize`.
However, for this PR we keep the old
code in place in order to allow for easy
regression testing with the benchmark JAR
like this:
> java -cp utils/bin/firrtl-benchmark.jar \
firrtl.benchmark.hot.SerializationBenchmark \
~/benchmarks/medium.pb 2 5 test
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Fix a bug where a type check would always yield true. This caused a
bug where allow/block-list annotations would be incorrectly applied to
all subtypes of ManipulateNames.
The tests are updated to check that this now works.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add testcase for empty message
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Add tests for the ManipulateNames transform.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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If a module has ports of type Bundle that are used in aggregate
connections in parent modules, Dedup cannot change the names of the
fields of the Bundle or it would change the semantics of the connection.
Dedup now detects this case and refrains from agnostifying the ports of
such modules to prevent this issue.
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* Add assume, assert, cover statements
* Assert submodule assumptions
* Add warning when removing verification statements
* Remove System Verilog behaviour emitter warning
* Add option to disable AssertSubmoduleAssumptions
* Document verification statements in the spec
The syntax for the new statements is
assert(clk, cond, en, msg)
assume(clk, cond, en, msg)
cover(clk, cond, en, msg)
With assert as a representative example, the semantics is as follows:
`clk` is the clock, `cond` is the expression being asserted, `en` is the
enable signal (if `en` is low then the assert is not checked) and `msg`
is a string message intended to be reported as an error message by the
model checker if the assertion fails.
In the Verilog emitter, the new statements are handled by a new
`formals` map, which groups the statements by clock domain. All model
checking statements are then emitted within the context of an `ifdef
FORMAL` block, which allows model checking tools (like Symbiyosys) to
utilize the statements while keeping them out of synthesis flows.
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Support Memory Initialization for Simulation and FPGA Flows
This adds a minimal annotation that allows users to
influence if memories are randomly initialized,
if all entries are initialized to the same scalar or
if each entry should be initialized to a different value.
We use the init block in order to initialize memories
which is supported by verilator as well as yosys
and has previously been used to randomize the initial
memory contents.
* LowerTypes: error when trying to split up a memory with MemoryInitAnnotation
Currently the MemoryInitAnnotation only works for
ground-type memories.
We catch misuse of this annotation at the point of
the firrtl compiler at which memories on non-ground type
get split up, i.e., the LowerTypes transform.
Chisel should try to prevent annotating non-ground
type memories in the frontend, but it is nice to
have an additional check.
* MemoryInitSpec: test JSON deserialization
* MemoryInitAnnotation: split up into three different annotations instead of exposing MemoryInitValue
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add attributes, ifdefs to emitter.
* Make ifdef API a little cleaner.
* Remove references to ifdefs.
* Remove more of the ifdef stuff I missed
* Fix up failing tests
* Add multiple attribute test case
* Remove tpe as a parameter from Annotations.
Some general refactoring.
* Add some documentation.
* Incorporate some feedback
* Expand some spaghetti code, add comments
* Fix type signature by removing it
* bug fix in test
* Fix unchecked type parameter matches in AddDescriptionNodes.
* use target to replace name
Co-authored-by: Paul Rigge <rigge@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Build ArrayBuffers in Block.mapStmt
* Have empty Block serialize as "skip"
The FIRRTL parser requires at least one indented line in each module.
Sometimes tests emit and parse modules with no contents; this ensures
there's always at least a "skip" in empty modules.
Also fix tests that expected certain skips
* Use var List as stack in Block.mapStmt impl
This replaces Iterator concatenation. In Scala 2.11, RHS recursion on
Iterators is not stack safe. This seems to have been fixed in 2.12 by
Scala PR 5033.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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{Lower,Upper}CaseNames Transforms (#1651)
* Revert "Add test of {Lower, Upper}CaseNames"
This reverts commit 93c078b8469bc55cd2d33147c33e2b5421fda9d9.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Revert "Add --change-name-case <lower|upper> option"
This reverts commit d3ab7e2db66fe3a63778f427dad6c08f64695ba5.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Revert "Add features.{LowerCaseNames, UpperCaseNames} transforms"
This reverts commit c8dcdacf313f19a4d0238be694478a325432edd4.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Revert "Refactor RemoveKeywordCollisions->ManipulateNames"
This reverts commit c534c5abae7b80a725ec9925569b3383b3c24a34.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- RenameMap Behavior
-- Prevent transitive renaming A -> B -> C (continueRenaming)
-- Prevent transitive renaming for self-renames
- Target
-- Override toString as serialize for CompleteTarget
-- Expansion of stripHierarchy to enable stripping InstanceTargets to become ModuleTargets
Annotations
-- Bugfix in extractComponents where Products were not iterated over
-- Converts renamed targets to local targets using Target.referringModule to preserve sticky behavior
- Eliminate Target Paths
-- Make DuplicationHelper use LinkedHashMap, as we iterate over its contents and convert to Seq in def makePathless
-- Add DupedResult to map original module to new module targets
-- Update renaming to record a map from all relative instance paths to original module, to new module target
-- Consumes DedupedResult to give better name to new duplicated module if it was originally deduplicated
-- Reorder modules in attempt to preserve original ordering, pre-deduplication
-- Move utility functions to object
-- Bugfix: add self-renames to prevent ofModule _ of target _ cannot be renamed to Vector(_, _, _, ...) errors
- Dedup
-- Changed NoDedupAnnotation to contain ModuleTarget, rather than ModuleName
-- Added DedupedResult to map original module to the duplicate module
-- Consumes DupedResult to pick better name, if it existed
-- Updates renaming to chain the following: instancify deduped modules, remap differently named internal signals, then remap AST modules
-- Move utility functions to object
-- Remove annotations as part of determination of dedup correctness
-- Bugfix: add instance renames so that deduped modules have their instances properly renamed
- Dead Code Elimination
-- Add deletion of ASTModules
- Tests
-- Morphism Spec to ensure Dedup -> EliminateTargetPaths and EliminateTargetPaths -> Dedup patterns work properly
-- Update existing tests to make sure they work properly
-- Add Dedup tests to demonstrate instance renaming bug, EliminateTargetPaths for ofModule rename bug, and update RenameMap tests
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Adam Izraelevitz <azidar@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Absorb WRef into Reference
* Absorb WSubField into SubField
* Absorb WSubIndex into SubIndex
* Absorb WSubAccess into SubAccess
* Absorb WDefInstance into DefInstance
------------------------- API CHANGE SEVERITY --------------------------
This is projected to not break source-level compatibility with any known
user code. However, it will break *binary* compatibility with all
existing user FIRRTL passes, as is generally allowed with major
releases of FIRRTL.
--------------------------- DESCRIPTION --------------------------------
Previously, there were several nodes in WIR.scala that had a one-to-one
correspondance with existing nodes in the standard firrtl.ir hierarchy.
These nodes would have a case class resembling the corresponding
standard IR node, but with the addition of one or more "analysis"
fields.
Since these fields (such as kind) represent helpful info that can be
invalidated or set to Unknown (e.g. UnknownKind for Kind), it does not
cause any issues to simply include these fields on any in-memory
representation of FIRRTL IR. Although other systems for tracking FIRRTL
analyses have evolved over time, the ubiquity of pattern-matching on
these fields has lead most core and custom transforms to be written
against WIR, rather than IR.
This PR unifies the IRs by adding the fields that would be in an
"augmented" WIR node directly into the corresponding IR node; i.e., the
"type" and "kind" fields from WRef are added directly to the definition
of the Reference case class, while these "repetitive" WIR case classes
are removed entirely.
-------------------- SOURCE-COMPATIBILITY ADAPTERS ---------------------
Several object methods are added to WIR.scala to maintain
source-compatiblity for passes that used WIR. These objects define
factory methods and unapply methods, so passes that relied on implicit
case class factories or pattern matching for the removed WIR types will
remain perfectly source-compatible. However, these do not guarantee
compatibility at the binary level.
The types of the removed WIR case classes are also added as type aliases
to the top-level firrtl package, which allows code that relies on
explicit constructor calls or reflection to retain source-compatibility.
Finally, additional explicit factory methods are added to the companion
objects of the newly-augmented IR case classes, which allows user code
to avoid having to specify any of the new analysis fields. Existing code
that created non-WIR IR nodes will be able to continue using the
previous factory signatures, which will cause all omitted analysis
fields to be set to Unknown.
---------------------- UNMITIGATED API CHANGES -------------------------
While passes that used WIR will be source-compatible with this change,
there is one significant change that affects any pass currently using
non-WIR IR: the signatures of pattern-matching cases for Reference,
SubField, SubIndex, SubAccess, and DefInstance must change to
accommodate the extra fields.
This cannot be worked at the API level due to restrictions on unapply
overloading, but it could theoretically be solved with macros or other
static rewriting. However, only four core transforms (RemoveProto,
ToWorkingIR, Dedup, and RemoveChirrtl) use non-WIR IR, and it is
expected that no user code currently relies on it, so the expected
migration strategy is simply to change the small fraction of code
relying on these nodes.
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If an annotation cannot be serialized by json4s, we should not throw
exceptions when doing trace-level logging.
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* RenameMap: remove implicit rename chaining
* RenameMap: remove trailing comma
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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