Fix parsing of info on multi-line registers (#1735)

For multi-line registers, the parsed source locator is located in a
different place in the concrete syntax tree than it is for other
Statements.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1 files changed, 23 insertions, 4 deletions

diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala
index 392be8cf..2ae5b430 100644
--- a/src/test/scala/firrtlTests/ParserSpec.scala
+++ b/src/test/scala/firrtlTests/ParserSpec.scala
@@ -3,7 +3,9 @@
 package firrtlTests
 
 import firrtl._
+import firrtl.ir._
 import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers._
 import org.scalacheck.Gen
 
 class ParserSpec extends FirrtlFlatSpec {
@@ -24,9 +26,12 @@ class ParserSpec extends FirrtlFlatSpec {
 
   private object RegTests {
     val prelude = Seq("circuit top :", "  module top :")
-    val reg = "    reg r : UInt<32>, clock"
+    val regName = "r"
+    val reg = s"    reg $regName : UInt<32>, clock"
     val reset = "reset => (radReset, UInt(\"hdeadbeef\"))"
-    val finfo = "@[Reg.scala:33:10]"
+    val sourceLocator = "Reg.scala 33:10"
+    val finfo = s"@[$sourceLocator]"
+    val fileInfo = FileInfo(StringLit(sourceLocator))
   }
 
   private object KeywordTests {
@@ -79,12 +84,26 @@ class ParserSpec extends FirrtlFlatSpec {
 
   it should "allow source locators with same-line reset" in {
     import RegTests._
-    firrtl.Parser.parse((prelude :+ s"${reg} with : (${reset}) $finfo" :+ "    wire a : UInt"))
+    val res = firrtl.Parser.parse((prelude :+ s"${reg} with : (${reset}) $finfo" :+ "    wire a : UInt"))
+    CircuitState(res, Nil) should containTree {
+      case DefRegister(`fileInfo`, `regName`, _,_,_,_) => true
+    }
   }
 
   it should "allow source locators with multi-line reset" in {
     import RegTests._
-    firrtl.Parser.parse((prelude :+ s"${reg} with :\n      (${reset}) $finfo"))
+    val res = firrtl.Parser.parse((prelude :+ s"${reg} with :\n      (${reset}) $finfo"))
+    CircuitState(res, Nil) should containTree {
+      case DefRegister(`fileInfo`, `regName`, _,_,_,_) => true
+    }
+  }
+
+  it should "allow source locators with no reset" in {
+    import RegTests._
+    val res = firrtl.Parser.parse((prelude :+ s"${reg} $finfo"))
+    CircuitState(res, Nil) should containTree {
+      case DefRegister(`fileInfo`, `regName`, _,_,_,_) => true
+    }
   }
 
   // ********** Keywords **********