diff options
| -rw-r--r-- | src/main/scala/firrtl/Visitor.scala | 9 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/ParserSpec.scala | 27 |
2 files changed, 28 insertions, 8 deletions
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala index 48a887de..76b5c2cf 100644 --- a/src/main/scala/firrtl/Visitor.scala +++ b/src/main/scala/firrtl/Visitor.scala @@ -304,16 +304,17 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w case "reg" => val name = ctx.id(0).getText val tpe = visitType(ctx.`type`()) - val (reset, init) = { + val (reset, init, rinfo) = { val rb = ctx.reset_block() if (rb != null) { val sr = rb.simple_reset.simple_reset0() - (visitExp(sr.exp(0)), visitExp(sr.exp(1))) + val innerInfo = if (info == NoInfo) visitInfo(Option(rb.info), ctx) else info + (visitExp(sr.exp(0)), visitExp(sr.exp(1)), innerInfo) } else - (UIntLiteral(0, IntWidth(1)), Reference(name, tpe)) + (UIntLiteral(0, IntWidth(1)), Reference(name, tpe), info) } - DefRegister(info, name, tpe, visitExp(ctx_exp(0)), reset, init) + DefRegister(rinfo, name, tpe, visitExp(ctx_exp(0)), reset, init) case "mem" => visitMem(ctx) case "cmem" => val (tpe, size) = visitCMemType(ctx.`type`()) diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala index 392be8cf..2ae5b430 100644 --- a/src/test/scala/firrtlTests/ParserSpec.scala +++ b/src/test/scala/firrtlTests/ParserSpec.scala @@ -3,7 +3,9 @@ package firrtlTests import firrtl._ +import firrtl.ir._ import firrtl.testutils._ +import firrtl.testutils.FirrtlCheckers._ import org.scalacheck.Gen class ParserSpec extends FirrtlFlatSpec { @@ -24,9 +26,12 @@ class ParserSpec extends FirrtlFlatSpec { private object RegTests { val prelude = Seq("circuit top :", " module top :") - val reg = " reg r : UInt<32>, clock" + val regName = "r" + val reg = s" reg $regName : UInt<32>, clock" val reset = "reset => (radReset, UInt(\"hdeadbeef\"))" - val finfo = "@[Reg.scala:33:10]" + val sourceLocator = "Reg.scala 33:10" + val finfo = s"@[$sourceLocator]" + val fileInfo = FileInfo(StringLit(sourceLocator)) } private object KeywordTests { @@ -79,12 +84,26 @@ class ParserSpec extends FirrtlFlatSpec { it should "allow source locators with same-line reset" in { import RegTests._ - firrtl.Parser.parse((prelude :+ s"${reg} with : (${reset}) $finfo" :+ " wire a : UInt")) + val res = firrtl.Parser.parse((prelude :+ s"${reg} with : (${reset}) $finfo" :+ " wire a : UInt")) + CircuitState(res, Nil) should containTree { + case DefRegister(`fileInfo`, `regName`, _,_,_,_) => true + } } it should "allow source locators with multi-line reset" in { import RegTests._ - firrtl.Parser.parse((prelude :+ s"${reg} with :\n (${reset}) $finfo")) + val res = firrtl.Parser.parse((prelude :+ s"${reg} with :\n (${reset}) $finfo")) + CircuitState(res, Nil) should containTree { + case DefRegister(`fileInfo`, `regName`, _,_,_,_) => true + } + } + + it should "allow source locators with no reset" in { + import RegTests._ + val res = firrtl.Parser.parse((prelude :+ s"${reg} $finfo")) + CircuitState(res, Nil) should containTree { + case DefRegister(`fileInfo`, `regName`, _,_,_,_) => true + } } // ********** Keywords ********** |