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authorAlbert Chen2020-07-23 14:31:11 -0700
committerGitHub2020-07-23 21:31:11 +0000
commite30c20d10ba47b11e06416e912ed89b6b6ce8e7b (patch)
treed64b76b035c22a924eca42b7c91e0db56b99e987 /src/test
parent1927dc6574b9eee315c8f24441df390f2ce793c7 (diff)
fix reduction op bug ConstantPropagation (#1746)
* add const prop bitwise reduction equivalence test * mask negative literals when propagating reduction * change widths * get rid of unnecessary if * add BigInt mask utility
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index d81f8687..653653d6 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -1629,6 +1629,19 @@ class ConstantPropagationEquivalenceSpec extends FirrtlFlatSpec {
firrtlEquivalenceTest(input, transforms)
}
+ "reduction of literals" should "be propagated" in {
+ val input =
+ s"""circuit ConstPropReductionTester :
+ | module ConstPropReductionTester :
+ | output out1 : UInt<1>
+ | output out2 : UInt<1>
+ | output out3 : UInt<1>
+ | out1 <= xorr(SInt<2>(-1))
+ | out2 <= andr(SInt<2>(-1))
+ | out3 <= orr(SInt<2>(-1))""".stripMargin
+ firrtlEquivalenceTest(input, transforms)
+ }
+
"addition of negative literals" should "be propagated" in {
val input =
s"""circuit AddTester :