diff options
| author | Kevin Laeufer | 2020-07-29 15:25:34 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-29 22:25:34 +0000 |
| commit | c02c9b7f33d67d8a65040c028395e881668294f6 (patch) | |
| tree | e6eaa4f2787e74759f4cfffa61f84bd08a03d4c2 /src/test | |
| parent | 3a6e352626915751b2b2a5d6aec4203fb8e83a1d (diff) | |
WiringTransform: fix non-determinism (#1799)
* WiringUtils.sinksToSources: make sinkInsts order deterministic
* WiringUtils: make owners a LinkedHashMap
* Wiring: only make something a Wire if it isn't a port already
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/WiringTests.scala | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala index 48089f0c..8ec6d5ce 100644 --- a/src/test/scala/firrtlTests/WiringTests.scala +++ b/src/test/scala/firrtlTests/WiringTests.scala @@ -83,9 +83,9 @@ class WiringTests extends FirrtlFlatSpec { | x.clock <= clock | inst d of D | d.clock <= clock - | d.r <= r - | r <= b.r | x.pin <= r + | r <= b.r + | d.r <= r | module B : | input clock: Clock | output r: UInt<5> @@ -169,9 +169,9 @@ class WiringTests extends FirrtlFlatSpec { | x.clock <= clock | inst d of D | d.clock <= clock - | d.r <= r - | r <= b.r | x.pin <= r + | r <= b.r + | d.r <= r | module B : | input clock: Clock | output r: UInt<5> @@ -256,9 +256,9 @@ class WiringTests extends FirrtlFlatSpec { | x.clock <= clock | inst d of D | d.clock <= clock - | d.r <= r - | r <= b.r | x.pin <= r + | r <= b.r + | d.r <= r | module B : | input clock: Clock | output r: UInt<5> |