From c02c9b7f33d67d8a65040c028395e881668294f6 Mon Sep 17 00:00:00 2001
From: Kevin Laeufer
Date: Wed, 29 Jul 2020 15:25:34 -0700
Subject: WiringTransform: fix non-determinism (#1799)

* WiringUtils.sinksToSources: make sinkInsts order deterministic

* WiringUtils: make owners a LinkedHashMap

* Wiring: only make something a Wire if it isn't a port already

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/test/scala/firrtlTests/WiringTests.scala | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index 48089f0c..8ec6d5ce 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -83,9 +83,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    x.clock <= clock
          |    inst d of D
          |    d.clock <= clock
-         |    d.r <= r
-         |    r <= b.r
          |    x.pin <= r
+         |    r <= b.r
+         |    d.r <= r
          |  module B :
          |    input clock: Clock
          |    output r: UInt<5>
@@ -169,9 +169,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    x.clock <= clock
          |    inst d of D
          |    d.clock <= clock
-         |    d.r <= r
-         |    r <= b.r
          |    x.pin <= r
+         |    r <= b.r
+         |    d.r <= r
          |  module B :
          |    input clock: Clock
          |    output r: UInt<5>
@@ -256,9 +256,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    x.clock <= clock
          |    inst d of D
          |    d.clock <= clock
-         |    d.r <= r
-         |    r <= b.r
          |    x.pin <= r
+         |    r <= b.r
+         |    d.r <= r
          |  module B :
          |    input clock: Clock
          |    output r: UInt<5>
-- 
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