diff options
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/WiringTests.scala | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala index 48089f0c..8ec6d5ce 100644 --- a/src/test/scala/firrtlTests/WiringTests.scala +++ b/src/test/scala/firrtlTests/WiringTests.scala @@ -83,9 +83,9 @@ class WiringTests extends FirrtlFlatSpec { | x.clock <= clock | inst d of D | d.clock <= clock - | d.r <= r - | r <= b.r | x.pin <= r + | r <= b.r + | d.r <= r | module B : | input clock: Clock | output r: UInt<5> @@ -169,9 +169,9 @@ class WiringTests extends FirrtlFlatSpec { | x.clock <= clock | inst d of D | d.clock <= clock - | d.r <= r - | r <= b.r | x.pin <= r + | r <= b.r + | d.r <= r | module B : | input clock: Clock | output r: UInt<5> @@ -256,9 +256,9 @@ class WiringTests extends FirrtlFlatSpec { | x.clock <= clock | inst d of D | d.clock <= clock - | d.r <= r - | r <= b.r | x.pin <= r + | r <= b.r + | d.r <= r | module B : | input clock: Clock | output r: UInt<5> |