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authorJack Koenig2020-06-23 11:10:12 -0700
committerAlbert Magyar2020-06-23 12:20:33 -0700
commitd1db9067309fe2d7765def39ac4085edfe53d7be (patch)
tree9750f6e7ceab61efd46326f39f3cd9fb8bf5da58 /src/test
parent8c9d8f68e038cd9e245dd66580af962267024de0 (diff)
Add support for ValidIf to ProtoBuf [de]serialization
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/ProtoBufSpec.scala10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala
index 743e00ef..14f94cb3 100644
--- a/src/test/scala/firrtlTests/ProtoBufSpec.scala
+++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala
@@ -6,6 +6,7 @@ import firrtl.FirrtlProtos.Firrtl
import firrtl._
import firrtl.ir._
import firrtl.testutils._
+import firrtl.Utils.BoolType
class ProtoBufSpec extends FirrtlFlatSpec {
@@ -201,4 +202,13 @@ class ProtoBufSpec extends FirrtlFlatSpec {
val port = ir.Port(ir.NoInfo, "reset", ir.Input, ir.ResetType)
FromProto.convert(ToProto.convert(port).build) should equal (port)
}
+
+ it should "support ValidIf" in {
+ val en = ir.Reference("en", BoolType, PortKind, SourceFlow)
+ val value = ir.Reference("x", UIntType(IntWidth(8)), PortKind, SourceFlow)
+ val vi = ir.ValidIf(en, value, value.tpe)
+ // Deserialized has almost nothing filled in
+ val expected = ir.ValidIf(ir.Reference("en"), ir.Reference("x"), UnknownType)
+ FromProto.convert(ToProto.convert(vi).build) should equal (expected)
+ }
}