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authorJack Koenig2020-06-23 11:10:12 -0700
committerAlbert Magyar2020-06-23 12:20:33 -0700
commitd1db9067309fe2d7765def39ac4085edfe53d7be (patch)
tree9750f6e7ceab61efd46326f39f3cd9fb8bf5da58 /src
parent8c9d8f68e038cd9e245dd66580af962267024de0 (diff)
Add support for ValidIf to ProtoBuf [de]serialization
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/proto/FromProto.scala4
-rw-r--r--src/main/scala/firrtl/proto/ToProto.scala5
-rw-r--r--src/test/scala/firrtlTests/ProtoBufSpec.scala10
3 files changed, 19 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/proto/FromProto.scala b/src/main/scala/firrtl/proto/FromProto.scala
index ef2ee5bd..ea4cec1f 100644
--- a/src/main/scala/firrtl/proto/FromProto.scala
+++ b/src/main/scala/firrtl/proto/FromProto.scala
@@ -94,6 +94,9 @@ object FromProto {
def convert(mux: Firrtl.Expression.Mux): ir.Mux =
ir.Mux(convert(mux.getCondition), convert(mux.getTValue), convert(mux.getFValue), ir.UnknownType)
+ def convert(validif: Firrtl.Expression.ValidIf): ir.ValidIf =
+ ir.ValidIf(convert(validif.getCondition), convert(validif.getValue), ir.UnknownType)
+
def convert(expr: Firrtl.Expression): ir.Expression = {
import Firrtl.Expression._
expr.getExpressionCase.getNumber match {
@@ -106,6 +109,7 @@ object FromProto {
case FIXED_LITERAL_FIELD_NUMBER => convert(expr.getFixedLiteral)
case PRIM_OP_FIELD_NUMBER => convert(expr.getPrimOp)
case MUX_FIELD_NUMBER => convert(expr.getMux)
+ case VALID_IF_FIELD_NUMBER => convert(expr.getValidIf)
}
}
diff --git a/src/main/scala/firrtl/proto/ToProto.scala b/src/main/scala/firrtl/proto/ToProto.scala
index c246656f..e2481d08 100644
--- a/src/main/scala/firrtl/proto/ToProto.scala
+++ b/src/main/scala/firrtl/proto/ToProto.scala
@@ -188,6 +188,11 @@ object ToProto {
.setTValue(convert(tval))
.setFValue(convert(fval))
eb.setMux(mb)
+ case ir.ValidIf(cond, value, _) =>
+ val vb = Firrtl.Expression.ValidIf.newBuilder()
+ .setCondition(convert(cond))
+ .setValue(convert(value))
+ eb.setValidIf(vb)
}
}
diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala
index 743e00ef..14f94cb3 100644
--- a/src/test/scala/firrtlTests/ProtoBufSpec.scala
+++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala
@@ -6,6 +6,7 @@ import firrtl.FirrtlProtos.Firrtl
import firrtl._
import firrtl.ir._
import firrtl.testutils._
+import firrtl.Utils.BoolType
class ProtoBufSpec extends FirrtlFlatSpec {
@@ -201,4 +202,13 @@ class ProtoBufSpec extends FirrtlFlatSpec {
val port = ir.Port(ir.NoInfo, "reset", ir.Input, ir.ResetType)
FromProto.convert(ToProto.convert(port).build) should equal (port)
}
+
+ it should "support ValidIf" in {
+ val en = ir.Reference("en", BoolType, PortKind, SourceFlow)
+ val value = ir.Reference("x", UIntType(IntWidth(8)), PortKind, SourceFlow)
+ val vi = ir.ValidIf(en, value, value.tpe)
+ // Deserialized has almost nothing filled in
+ val expected = ir.ValidIf(ir.Reference("en"), ir.Reference("x"), UnknownType)
+ FromProto.convert(ToProto.convert(vi).build) should equal (expected)
+ }
}