1 files changed, 10 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala
index 743e00ef..14f94cb3 100644
--- a/src/test/scala/firrtlTests/ProtoBufSpec.scala
+++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala
@@ -6,6 +6,7 @@ import firrtl.FirrtlProtos.Firrtl
 import firrtl._
 import firrtl.ir._
 import firrtl.testutils._
+import firrtl.Utils.BoolType
 
 class ProtoBufSpec extends FirrtlFlatSpec {
 
@@ -201,4 +202,13 @@ class ProtoBufSpec extends FirrtlFlatSpec {
     val port = ir.Port(ir.NoInfo, "reset", ir.Input, ir.ResetType)
     FromProto.convert(ToProto.convert(port).build) should equal (port)
   }
+
+  it should "support ValidIf" in {
+    val en = ir.Reference("en", BoolType, PortKind, SourceFlow)
+    val value = ir.Reference("x", UIntType(IntWidth(8)), PortKind, SourceFlow)
+    val vi = ir.ValidIf(en, value, value.tpe)
+    // Deserialized has almost nothing filled in
+    val expected = ir.ValidIf(ir.Reference("en"), ir.Reference("x"), UnknownType)
+    FromProto.convert(ToProto.convert(vi).build) should equal (expected)
+  }
 }