Integrate new transforms with firrtl.stage.Forms (#1754)

Move new transforms, recently added, into existing or new sets of
transforms (defined in firrtl.stage.Forms).

One transform is a mandatory low FIRRTL optimization:

  - firrtl.transforms.LegalizeAndReductionsTransform

Previously, this was included as a prerequisite of all Verilog
emitters (minimum, normal, and SystemVerilog).

Two transforms associated with converting and removing the new
verification statements are moved into a new set of transforms,
AssertsRemoved:

  - firrtl.transforms.formal.ConvertAsserts
  - firrtl.transforms.formal.RemoveVerificationStatements

Previously, these transforms were directly added as prerequisites to
the minimum Verilog and normal Verilog emitter, but not the
SystemVerilog emitter.

The designation of inputForm=LowForm for legacy, custom transforms is
updated to include assertion removal transforms as part of their
optionalPrerequisites. This has the effect of continuing to cause
inputForm=LowForm transforms to run as late as possible (right before
the low FIRRTL, minimum Verilog, Verilog, or SystemVeriog emitter).

Tests are updated to reflect the new order in both CustomTransformSpec
and LoweringCompilersSpec.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

2 files changed, 5 insertions, 10 deletions

diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index 9141a9f7..3e5fd254 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -150,13 +150,6 @@ class CustomTransformSpec extends FirrtlFlatSpec {
 
   they should "run right before the emitter* when inputForm=LowForm" in {
 
-    val locationMap = Map(
-      Dependency[LowFirrtlEmitter]      -> Dependency[LowFirrtlEmitter],
-      Dependency[MinimumVerilogEmitter] -> Dependency(ConvertAsserts),
-      Dependency[VerilogEmitter]        -> Dependency(ConvertAsserts),
-      Dependency[SystemVerilogEmitter]  -> Dependency[LegalizeAndReductionsTransform]
-    )
-
     Seq(
       Dependency[LowFirrtlEmitter],
       Dependency[MinimumVerilogEmitter],
@@ -170,7 +163,7 @@ class CustomTransformSpec extends FirrtlFlatSpec {
         .flattenedTransformOrder
         .map(Dependency.fromTransform)
         .sliding(2)
-        .toList should contain (Seq(custom, locationMap(emitter)))
+        .toList should contain (Seq(custom, emitter))
     }
 
   }
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index 7df621d3..854763f1 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -192,7 +192,8 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
     val tm = new TransformManager(Forms.LowFormMinimumOptimized, Forms.LowForm)
     val patches = Seq(
       Add(4, Seq(Dependency(firrtl.passes.ResolveFlows))),
-      Add(5, Seq(Dependency(firrtl.passes.ResolveKinds)))
+      Add(6, Seq(Dependency[firrtl.transforms.LegalizeAndReductionsTransform],
+                 Dependency(firrtl.passes.ResolveKinds)))
     )
     compare(legacyTransforms(new MinimumLowFirrtlOptimization), tm, patches)
   }
@@ -204,7 +205,8 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
     val patches = Seq(
       Add(6, Seq(Dependency(firrtl.passes.ResolveFlows))),
       Add(7, Seq(Dependency(firrtl.passes.Legalize))),
-      Add(8, Seq(Dependency(firrtl.passes.ResolveKinds)))
+      Add(8, Seq(Dependency[firrtl.transforms.LegalizeAndReductionsTransform],
+                 Dependency(firrtl.passes.ResolveKinds)))
     )
     compare(legacyTransforms(new LowFirrtlOptimization), tm, patches)
   }