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-rw-r--r--src/main/scala/firrtl/Compiler.scala2
-rw-r--r--src/main/scala/firrtl/Emitter.scala19
-rw-r--r--src/main/scala/firrtl/stage/Forms.scala7
-rw-r--r--src/test/scala/firrtlTests/CustomTransformSpec.scala9
-rw-r--r--src/test/scala/firrtlTests/LoweringCompilersSpec.scala6
5 files changed, 17 insertions, 26 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 54380875..bed1b6d4 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -313,7 +313,7 @@ trait Transform extends TransformLike[CircuitState] with DependencyAPI[Transform
}
override def optionalPrerequisites: Seq[Dependency[Transform]] = inputForm match {
- case L => Forms.LowFormOptimized
+ case L => Forms.LowFormOptimized ++ Forms.AssertsRemoved
case _ => Seq.empty
}
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 850c8ca1..3329cf9e 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -7,16 +7,15 @@ import java.io.Writer
import scala.collection.mutable
import firrtl.ir._
import firrtl.passes._
-import firrtl.transforms.{FixAddingNegativeLiterals, LegalizeAndReductionsTransform}
+import firrtl.transforms.FixAddingNegativeLiterals
import firrtl.annotations._
import firrtl.traversals.Foreachers._
import firrtl.PrimOps._
import firrtl.WrappedExpression._
import Utils._
import MemPortUtils.{memPortField, memType}
-import firrtl.options.{Dependency, HasShellOptions, PhaseException, ShellOption, Unserializable}
+import firrtl.options.{HasShellOptions, PhaseException, ShellOption, Unserializable}
import firrtl.stage.{RunFirrtlTransformAnnotation, TransformManager}
-import firrtl.transforms.formal.{RemoveVerificationStatements, ConvertAsserts}
// Datastructures
import scala.collection.mutable.ArrayBuffer
@@ -181,10 +180,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
def inputForm = LowForm
def outputForm = LowForm
- override def prerequisites =
- Dependency(ConvertAsserts) +:
- Dependency[RemoveVerificationStatements] +:
- Dependency[LegalizeAndReductionsTransform] +:
+ override def prerequisites = firrtl.stage.Forms.AssertsRemoved ++
firrtl.stage.Forms.LowFormOptimized
override def optionalPrerequisiteOf = Seq.empty
@@ -1254,10 +1250,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
class MinimumVerilogEmitter extends VerilogEmitter with Emitter {
- override def prerequisites =
- Dependency(ConvertAsserts) +:
- Dependency[RemoveVerificationStatements] +:
- Dependency[LegalizeAndReductionsTransform] +:
+ override def prerequisites = firrtl.stage.Forms.AssertsRemoved ++
firrtl.stage.Forms.LowFormMinimumOptimized
override def transforms = new TransformManager(firrtl.stage.Forms.VerilogMinimumOptimized, prerequisites)
@@ -1268,9 +1261,7 @@ class MinimumVerilogEmitter extends VerilogEmitter with Emitter {
class SystemVerilogEmitter extends VerilogEmitter {
override val outputSuffix: String = ".sv"
- override def prerequisites =
- Dependency[LegalizeAndReductionsTransform] +:
- firrtl.stage.Forms.LowFormOptimized
+ override def prerequisites = firrtl.stage.Forms.LowFormOptimized
override def addFormalStatement(formals: mutable.Map[Expression, ArrayBuffer[Seq[Any]]],
clk: Expression, en: Expression,
diff --git a/src/main/scala/firrtl/stage/Forms.scala b/src/main/scala/firrtl/stage/Forms.scala
index e6ed9603..933db4f4 100644
--- a/src/main/scala/firrtl/stage/Forms.scala
+++ b/src/main/scala/firrtl/stage/Forms.scala
@@ -72,7 +72,8 @@ object Forms {
Seq( Dependency(passes.RemoveValidIf),
Dependency(passes.PadWidths),
Dependency(passes.memlib.VerilogMemDelays),
- Dependency(passes.SplitExpressions) )
+ Dependency(passes.SplitExpressions),
+ Dependency[firrtl.transforms.LegalizeAndReductionsTransform] )
val LowFormOptimized: Seq[TransformDependency] = LowFormMinimumOptimized ++
Seq( Dependency[firrtl.transforms.ConstantPropagation],
@@ -95,6 +96,10 @@ object Forms {
val VerilogOptimized: Seq[TransformDependency] = LowFormOptimized ++ VerilogMinimumOptimized
+ val AssertsRemoved: Seq[TransformDependency] =
+ Seq( Dependency(firrtl.transforms.formal.ConvertAsserts),
+ Dependency[firrtl.transforms.formal.RemoveVerificationStatements] )
+
val BackendEmitters =
Seq( Dependency[VerilogEmitter],
Dependency[MinimumVerilogEmitter],
diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index 9141a9f7..3e5fd254 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -150,13 +150,6 @@ class CustomTransformSpec extends FirrtlFlatSpec {
they should "run right before the emitter* when inputForm=LowForm" in {
- val locationMap = Map(
- Dependency[LowFirrtlEmitter] -> Dependency[LowFirrtlEmitter],
- Dependency[MinimumVerilogEmitter] -> Dependency(ConvertAsserts),
- Dependency[VerilogEmitter] -> Dependency(ConvertAsserts),
- Dependency[SystemVerilogEmitter] -> Dependency[LegalizeAndReductionsTransform]
- )
-
Seq(
Dependency[LowFirrtlEmitter],
Dependency[MinimumVerilogEmitter],
@@ -170,7 +163,7 @@ class CustomTransformSpec extends FirrtlFlatSpec {
.flattenedTransformOrder
.map(Dependency.fromTransform)
.sliding(2)
- .toList should contain (Seq(custom, locationMap(emitter)))
+ .toList should contain (Seq(custom, emitter))
}
}
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index 7df621d3..854763f1 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -192,7 +192,8 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
val tm = new TransformManager(Forms.LowFormMinimumOptimized, Forms.LowForm)
val patches = Seq(
Add(4, Seq(Dependency(firrtl.passes.ResolveFlows))),
- Add(5, Seq(Dependency(firrtl.passes.ResolveKinds)))
+ Add(6, Seq(Dependency[firrtl.transforms.LegalizeAndReductionsTransform],
+ Dependency(firrtl.passes.ResolveKinds)))
)
compare(legacyTransforms(new MinimumLowFirrtlOptimization), tm, patches)
}
@@ -204,7 +205,8 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
val patches = Seq(
Add(6, Seq(Dependency(firrtl.passes.ResolveFlows))),
Add(7, Seq(Dependency(firrtl.passes.Legalize))),
- Add(8, Seq(Dependency(firrtl.passes.ResolveKinds)))
+ Add(8, Seq(Dependency[firrtl.transforms.LegalizeAndReductionsTransform],
+ Dependency(firrtl.passes.ResolveKinds)))
)
compare(legacyTransforms(new LowFirrtlOptimization), tm, patches)
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 20:37:48 +0000