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AgeCommit message (Expand)Author
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-19Don't use declaration-assigns for wires representing mem ports (#2189)Albert Magyar
2021-04-16Make InferTypes error on enable conditions > 1-bit wide (#2182)Jack Koenig
2021-04-16Fix signedness of xor const prop with zero (#2179)Fabian Schuiki
2021-04-06Deprecate InlineCasts, add InlineAcrossCasts (#2146)Jack Koenig
2021-04-05Add test for SeparateWriteClocksAlbert Magyar
2021-04-05Add tests for same-address readwrite inferenceAlbert Magyar
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
2021-03-27Add NoConstantPropagationAnnotation to disable constatnt propagation (#2150)Jiuyang Liu
2021-03-26Fix bug in zero-width memory removal (#2153)Schuyler Eldridge
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
2021-03-18Ensure InlineCasts does not inline complex Expressions (#2130)Jack Koenig
2021-03-16Fix issue where inlined cvt could cause crash (#2124)Jack Koenig
2021-03-14Fix width of constant propagation of SInt with zero (#2120)Jack Koenig
2021-03-14Fix cat of zero-width SInt (#2116)Jack Koenig
2021-03-11Fix CSESubAccesses for SubAccesses with flips (#2112)Jack Koenig
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
2021-03-09SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)Kevin Laeufer
2021-03-08SMT: memory port inout fields cannot be used as RHS expressions (#2105)Kevin Laeufer
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
2021-03-04CSE SubAccesses (#2099)Jack Koenig
2021-03-03Fix ProtoBuf conversions for Verification IR (#2100)Deborah Soung
2021-03-02Remove Scala 2.11 (#2062)Jack Koenig
2021-03-02Fix CI Checks (#2097)Jack Koenig
2021-02-17ExpandWhens: ensure that statement names are maintained (#2082)Kevin Laeufer
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
2021-02-16Add MustDeduplicateTransformJack Koenig
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
2021-01-28Stop padding multiply and divide ops (#2058)Jack Koenig
2021-01-20Add --dont-fold option to disable folding prim ops (#2040)Schuyler Eldridge
2021-01-19Restore scalafmt CI check (#2047)Jack Koenig
2021-01-19smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)Kevin Laeufer
2020-12-15Improve performance of LowerTypes renaming (#2024)Jack Koenig
2020-12-02smt: add support for uninterpreted ext modules (#1994)Kevin Laeufer
2020-12-02Fix subaccess (#1984)Jiuyang Liu
2020-11-30Add SortModules Transform (#1905)Schuyler Eldridge
2020-11-12Fix RemoveWires handling of invalidated non-UInt wires (#1949)Jack Koenig
2020-11-11smt: add support for write-first memories (#1948)Kevin Laeufer
2020-11-10Fix SMT Memory Bug (#1942)Kevin Laeufer
2020-11-09smt: ensure that all signals have a unique name (#1943)Kevin Laeufer
2020-10-26fix for LoweringCompilersSpec.Jiuyang liu
2020-10-26fix a test not detecting verilog name conflicts.Jiuyang liu
2020-10-01Fix "fix" for negative literals > 32 bitsJack Koenig
2020-09-30Add test for chaining RW-port rdata as wdata of another memAlbert Magyar
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-09-15Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)Jack Koenig
2020-09-14Hit connect case in DedupModuleTests (#1716)Schuyler Eldridge
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