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authorJack Koenig2021-03-10 20:14:03 -0800
committerGitHub2021-03-11 04:14:03 +0000
commited1eb88d6ccdccd4b5802676cd8b69f5cc357e4f (patch)
treec844703527c883a03f13048ec722f0a339ac4867 /src/test
parentaa24fe3ece6edcd1c121d6aa6860b6de825bb381 (diff)
Fix CSESubAccesses for SubAccesses with flips (#2112)
The flow of a LHS SubAccess node may still be SourceFlow if the type of the Vec element has a flip. Tweak the logic of CSESubAccesses to check every Expression flow while recursing instead of just the flow of the final SubAccess. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/transforms/CSESubAccessesSpec.scala36
1 files changed, 36 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/transforms/CSESubAccessesSpec.scala b/src/test/scala/firrtlTests/transforms/CSESubAccessesSpec.scala
index 55ce07df..f7d67026 100644
--- a/src/test/scala/firrtlTests/transforms/CSESubAccessesSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/CSESubAccessesSpec.scala
@@ -184,4 +184,40 @@ class CSESubAccessesSpec extends FirrtlFlatSpec {
compile(input) should be(parse(expected).serialize)
}
+ it should "ignore flipped LHS SubAccesses" in {
+ val input = circuit(
+ s"""|input in : { foo : UInt<8> }
+ |input idx : UInt<1>
+ |input out : { flip foo : UInt<8> }[2]
+ |out[0].foo <= UInt(0)
+ |out[1].foo <= UInt(0)
+ |out[idx].foo <= in.foo"""
+ )
+ val expected = circuit(
+ s"""|input in : { foo : UInt<8> }
+ |input idx : UInt<1>
+ |input out : { flip foo : UInt<8> }[2]
+ |out[0].foo <= UInt(0)
+ |out[1].foo <= UInt(0)
+ |out[idx].foo <= in.foo"""
+ )
+ compile(input) should be(parse(expected).serialize)
+ }
+
+ it should "ignore SubAccesses of bidirectional aggregates" in {
+ val input = circuit(
+ s"""|input in : { flip foo : UInt<8>, bar : UInt<8> }
+ |input idx : UInt<2>
+ |output out : { flip foo : UInt<8>, bar : UInt<8> }[4]
+ |out[idx] <= in"""
+ )
+ val expected = circuit(
+ s"""|input in : { flip foo : UInt<8>, bar : UInt<8> }
+ |input idx : UInt<2>
+ |output out : { flip foo : UInt<8>, bar : UInt<8> }[4]
+ |out[idx] <= in"""
+ )
+ compile(input) should be(parse(expected).serialize)
+ }
+
}