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authorDeborah Soung2021-03-03 16:45:49 -0800
committerGitHub2021-03-03 16:45:49 -0800
commit5be1abb4c654279762a463a861526ce4e0c48035 (patch)
tree6895b0e53cb59436dc7df8bb37d53efc05abf398 /src/test
parent38dc5401ea875037e23bbbe998fb1b0f9aef7334 (diff)
Fix ProtoBuf conversions for Verification IR (#2100)
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/ProtoBufSpec.scala13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala
index d56ef7b1..e5909944 100644
--- a/src/test/scala/firrtlTests/ProtoBufSpec.scala
+++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala
@@ -218,6 +218,19 @@ class ProtoBufSpec extends FirrtlFlatSpec {
FromProto.convert(ToProto.convert(vi).build) should equal(expected)
}
+ it should "support Verification" in {
+ val clk = ir.Reference("clk", UnknownType)
+ val pred = ir.Reference("pred", UnknownType)
+ val en = ir.Reference("en", UnknownType)
+ val assert = ir.Verification(ir.Formal.Assert, ir.NoInfo, clk, pred, en, ir.StringLit("my assert message"))
+ val assume = ir.Verification(ir.Formal.Assume, ir.NoInfo, clk, pred, en, ir.StringLit("my assume message"))
+ val cover = ir.Verification(ir.Formal.Cover, ir.NoInfo, clk, pred, en, ir.StringLit("my cover message"))
+
+ FromProto.convert(ToProto.convert(assert).head.build) should equal(assert)
+ FromProto.convert(ToProto.convert(assume).head.build) should equal(assume)
+ FromProto.convert(ToProto.convert(cover).head.build) should equal(cover)
+ }
+
it should "appropriately escape and unescape FileInfo strings" in {
val pairs = Seq(
"test\\ntest" -> "test\ntest",