Memlib Refactor (#2191)

* remove all deprecations, switch to new API.

* Add MemLibOutConfigFileAnnotation to replace ConfWriter.

* Inline CreateMemoryAnnotations in ReplSeqMem.

* Dont use ConfWriter anymore.

* Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation.

* Fix for review.

0. Since DependencyAPI only initiate transform only once, ListBuffer is
   dangerous to use, remove defAnnotatedMemories from Transform.
1. Add trait HasAnnotatedMemories to store ListBuffer,
   MemLibOutConfigFileAnnotation also extends from which now.

* Use two annotations converting and storing DefMemory.

0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation
   creating PinAnnotation.
1. add DumpMemoryAnnotations to convert from
   AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation
2. refactor MemLibOutConfigFileAnnotation and remove
   HasAnnotatedMemories
3. add private AnnotatedMemoriesCollectorAnnotation to store mutable
   DefAnnotatedMemory
4. change ReplSeqMem to SeqTransform

* Fix for review.

0. replace AnnotatedMemoriesCollectorAnnotation with immutable
   AnnotatedMemoriesAnnotation.
1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute.

* private functions in ReplaceMemMacros transform.

* scalafmt

* remove ConfWriter API.

1 files changed, 18 insertions, 18 deletions

diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index 84709a21..4e00cb3a 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -3,14 +3,13 @@
 package firrtlTests
 
 import firrtl._
+import firrtl.annotations._
 import firrtl.ir._
 import firrtl.passes._
-import firrtl.transforms._
 import firrtl.passes.memlib._
-import firrtl.FileUtils
+import firrtl.testutils.FirrtlCheckers._
 import firrtl.testutils._
-import annotations._
-import FirrtlCheckers._
+import firrtl.transforms._
 
 class ReplSeqMemSpec extends SimpleTransformSpec {
   def emitter = new LowFirrtlEmitter
@@ -30,10 +29,11 @@ class ReplSeqMemSpec extends SimpleTransformSpec {
     }
   )
 
-  @deprecated("API will be changed in 1.5.", "FIRRTL 1.4")
-  def checkMemConf(filename: String, mems: Set[MemConf]) {
+  def checkMemConf(circuitState: CircuitState, mems: Set[MemConf]) {
     // Read the mem conf
-    val text = FileUtils.getText(filename)
+    val text = circuitState.annotations.collectFirst {
+      case a: MemLibOutConfigFileAnnotation => a.getBytes.map(_.toChar).mkString
+    }.get
     // Verify that this does not throw an exception
     val fromConf = MemConf.fromString(text)
     // Verify the mems in the conf are the same as the expected ones
@@ -75,7 +75,7 @@ circuit Top :
     // Check correctness of firrtl
     parse(res.getEmittedCircuit.value)
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -100,7 +100,7 @@ circuit Top :
     // Check correctness of firrtl
     parse(res.getEmittedCircuit.value)
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -128,7 +128,7 @@ circuit CustomMemory :
     // Check correctness of firrtl
     parse(res.getEmittedCircuit.value)
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -156,7 +156,7 @@ circuit CustomMemory :
     // Check correctness of firrtl
     parse(res.getEmittedCircuit.value)
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -245,7 +245,7 @@ circuit CustomMemory :
     }
     numExtMods should be(2)
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -292,7 +292,7 @@ circuit CustomMemory :
     }
     numExtMods should be(2)
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -354,7 +354,7 @@ circuit CustomMemory :
     //   would be 3 ExtModules
     numExtMods should be(2)
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -414,7 +414,7 @@ circuit CustomMemory :
     val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos))
     res.getEmittedCircuit.value shouldNot include("mask")
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -444,7 +444,7 @@ circuit CustomMemory :
     res should containLine("mem.W0_mask_0 <= validif(io_en, io_mask_0)")
     res should containLine("mem.W0_mask_1 <= validif(io_en, io_mask_1)")
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -478,7 +478,7 @@ circuit CustomMemory :
     res should containLine("mem.RW0_wmask_0 <= validif(io_en, io_mask_0)")
     res should containLine("mem.RW0_wmask_1 <= validif(io_en, io_mask_1)")
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -499,7 +499,7 @@ circuit NoMemsHere :
     val annos = Seq(ReplSeqMemAnnotation.parse("-c:CustomMemory:-o:" + confLoc), InferReadWriteAnnotation)
     val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos))
     // Check the emitted conf
-    checkMemConf(confLoc, mems)
+    checkMemConf(res, mems)
     (new java.io.File(confLoc)).delete()
   }