diff options
| author | Schuyler Eldridge | 2020-09-14 15:02:15 -0400 |
|---|---|---|
| committer | GitHub | 2020-09-14 19:02:15 +0000 |
| commit | 5f410f0e4774121932d644f31fde83b9b8ed78be (patch) | |
| tree | b1331ae34c838c78a3951f0373e18b872e899050 /src/test | |
| parent | c31626ea84cb3f6bb35f001f4da180b36bef1092 (diff) | |
Hit connect case in DedupModuleTests (#1716)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/transforms/DedupTests.scala | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala index 8c2835dd..8213cb84 100644 --- a/src/test/scala/firrtlTests/transforms/DedupTests.scala +++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala @@ -256,7 +256,7 @@ class DedupModuleTests extends HighTransformSpec { execute(diff_params, diff_params, Seq.empty) } - "Modules with aggregate ports that are bulk connected" should "NOT dedup if their port names differ" in { + "Modules with aggregate ports that are (partial)? connected" should "NOT dedup if their port names differ" in { val input = """ |circuit FooAndBarModule : @@ -271,13 +271,13 @@ class DedupModuleTests extends HighTransformSpec { | inst foo of FooModule | inst bar of BarModule | io.foo <- foo.io - | io.bar <- bar.io + | io.bar <= bar.io |""".stripMargin val check = input execute(input, check, Seq.empty) } - "Modules with aggregate ports that are bulk connected" should "dedup if their port names are the same" in { + "Modules with aggregate ports that are (partial)? connected" should "dedup if their port names are the same" in { val input = """ |circuit FooAndBarModule : @@ -288,10 +288,10 @@ class DedupModuleTests extends HighTransformSpec { | output io : {flip foo : UInt<1>, fuzz : UInt<1>} | io.fuzz <= io.foo | module FooAndBarModule : - | output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip bar : UInt<1>, buzz : UInt<1>}} + | output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip foo : UInt<1>, fuzz : UInt<1>}} | inst foo of FooModule | inst bar of BarModule - | io.foo <- foo.io + | io.foo <= foo.io | io.bar <- bar.io |""".stripMargin val check = @@ -301,10 +301,10 @@ class DedupModuleTests extends HighTransformSpec { | output io : {flip foo : UInt<1>, fuzz : UInt<1>} | io.fuzz <= io.foo | module FooAndBarModule : - | output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip bar : UInt<1>, buzz : UInt<1>}} + | output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip foo : UInt<1>, fuzz : UInt<1>}} | inst foo of FooModule | inst bar of FooModule - | io.foo <- foo.io + | io.foo <= foo.io | io.bar <- bar.io |""".stripMargin execute(input, check, Seq.empty) |