diff options
| author | Albert Magyar | 2021-04-19 08:50:18 -0700 |
|---|---|---|
| committer | GitHub | 2021-04-19 08:50:18 -0700 |
| commit | 72afdefd0f2e894d5dfe346aae36a23b2fd25def (patch) | |
| tree | 7511c50f8064a16ddc0b3f605a619e32d50231f1 /src/test | |
| parent | bf1cf3d2db49195d031f89594baebcc9f307659e (diff) | |
Don't use declaration-assigns for wires representing mem ports (#2189)
* Fixes #2173
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/InfoSpec.scala | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala index db4828f6..43fb6ee1 100644 --- a/src/test/scala/firrtlTests/InfoSpec.scala +++ b/src/test/scala/firrtlTests/InfoSpec.scala @@ -91,11 +91,11 @@ class InfoSpec extends FirrtlFlatSpec with FirrtlMatchers { result should containTree { case DefMemory(Info1, "m", _, _, _, _, _, _, _, _) => true } result should containLine(s"reg [7:0] m [0:31]; //$Info1") result should containLine(s"wire [7:0] m_r_data; //$Info1") - result should containLine(s"wire [4:0] m_r_addr = addr; //$Info1") - result should containLine(s"wire [7:0] m_w_data = 8'h0; //$Info1") - result should containLine(s"wire [4:0] m_w_addr = addr; //$Info1") - result should containLine(s"wire m_w_mask = 1'h0; //$Info1") - result should containLine(s"wire m_w_en = 1'h0; //$Info1") + result should containLine(s"wire [4:0] m_r_addr; //$Info1") + result should containLine(s"wire [7:0] m_w_data; //$Info1") + result should containLine(s"wire [4:0] m_w_addr; //$Info1") + result should containLine(s"wire m_w_mask; //$Info1") + result should containLine(s"wire m_w_en; //$Info1") result should containLine(s"assign m_r_data = m[m_r_addr]; //$Info1") result should containLine(s"m[m_w_addr] <= m_w_data; //$Info1") } |