Restore scalafmt CI check (#2047)

Fix scalafmtCheckAll failures that snuck through

1 files changed, 12 insertions, 11 deletions

diff --git a/src/test/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystemPassSpec.scala b/src/test/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystemPassSpec.scala
index 7dc5298c..e9254d7f 100644
--- a/src/test/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystemPassSpec.scala
+++ b/src/test/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystemPassSpec.scala
@@ -6,8 +6,9 @@ import firrtl.annotations.{CircuitTarget, PresetAnnotation}
 import firrtl.options.Dependency
 import firrtl.testutils.LeanTransformSpec
 
-class FirrtlToTransitionSystemPassSpec extends LeanTransformSpec(Seq(Dependency(firrtl.backends.experimental.smt.FirrtlToTransitionSystem))) {
-  behavior of "FirrtlToTransitionSystem"
+class FirrtlToTransitionSystemPassSpec
+    extends LeanTransformSpec(Seq(Dependency(firrtl.backends.experimental.smt.FirrtlToTransitionSystem))) {
+  behavior.of("FirrtlToTransitionSystem")
 
   it should "support preset wires" in {
     // In order to give registers an initial wire, we use preset annotated resets.
@@ -16,18 +17,18 @@ class FirrtlToTransitionSystemPassSpec extends LeanTransformSpec(Seq(Dependency(
     // In Chisel this generates a node which needs to be removed.
 
     val src = """circuit ModuleAB :
-      |  module ModuleAB :
-      |    input clock : Clock
-      |    node _T = asAsyncReset(UInt<1>("h0"))
-      |    node preset = _T
-      |    reg REG : UInt<1>, clock with :
-      |      reset => (preset, UInt<1>("h0"))
-      |    assert(clock, UInt(1), not(REG), "REG == 0")
-      |""".stripMargin
+                |  module ModuleAB :
+                |    input clock : Clock
+                |    node _T = asAsyncReset(UInt<1>("h0"))
+                |    node preset = _T
+                |    reg REG : UInt<1>, clock with :
+                |      reset => (preset, UInt<1>("h0"))
+                |    assert(clock, UInt(1), not(REG), "REG == 0")
+                |""".stripMargin
     val anno = PresetAnnotation(CircuitTarget("ModuleAB").module("ModuleAB").ref("preset"))
 
     val result = compile(src, List(anno))
-    val sys = result.annotations.collectFirst{ case TransitionSystemAnnotation(sys) => sys }.get
+    val sys = result.annotations.collectFirst { case TransitionSystemAnnotation(sys) => sys }.get
     assert(sys.states.head.init.isDefined)
   }
 }