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2022-03-04[spec] Remove FIRRTL Specification (#2488)Schuyler Eldridge
This removes the FIRRTL specification as this now lives in its own repository: https://github.com/chipsalliance/firrtl-spec All git history (excluding binary updates to spec.pdf) have been migrated to the new repository. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-03-01Convert firrtl specification to Markdown file (#2236)Jared Barocsi
- Convert FIRRTL spec to Markdown file. - Add PDF generation via pandoc. - Remove old LaTeX specification. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-11-12Update spec on extmodule with defname, parameter (#2413)Schuyler Eldridge
Add defname, parameter to extmodule spec, NFC Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-09-24spec: Fix formatting of example of memory port types. (#2368)Richard Xia
8abf3085e3efb2b6dd3e123f13577b367d3f2695 reordered the fields, but it unintentionally placed a closing brace before the actual end of the write port type. This moves the brace to the end of the port. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-08-05Fix Specification Memory Port Types (#2319)Schuyler Eldridge
Correct incorrect type specified for memories in the FIRRTL specification. This is important because the memory type determines what is a legal bundle to try to connect to a memory port. I based this off of FIRRTL accepting the following circuit: circuit MemOrder: module MemOrder: input r: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip data : UInt<1>} input w: {addr : UInt<3>, en : UInt<1>, clk : Clock, data : UInt<1>, mask : UInt<1>} input rw: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip rdata : UInt<1>, wmode : UInt<1>, wdata : UInt<1>, wmask : UInt<1>} mem memory: data-type => UInt<1> depth => 8 reader => r writer => w readwriter => rw read-latency => 1 write-latency => 1 read-under-write => undefined memory.r <= r memory.w <= w memory.rw <= rw Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-08-02Update spec to disallow 0-bit mux sel (#2305)Schuyler Eldridge
Change the FIRRTL spec to disallow a zero-width multiplexer select. Clarify that the select line can be either one-bit or zero-bit, but will infer to one-bit. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-30Relax spec on 0-bit mux select, use SFC behaviorSchuyler Eldridge
Change the FIRRTL specification document to allow for 0-bit mux selects. The existing ZeroWidths pass will promote these to a 1-bit, 0-valued select signal (which effectively means that the mux can be optimized away to just the false path). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-06-21[spec] Explicit widths may be non-negative, not just positive (#2277)Albert Magyar
* Fixes #2206
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
* firrtl: add optional statement labels for stop, printf, assert, assume and cover * test: parsing of statement labels * ir: ensure that name is properly retained * SymbolTable: add support for labled statements * test: parsing statement labels * test: lower types name collisions with named statements * ignore empty names * Inline: deal with named and unnamed statements * RemoveWires: treat stop, printf and verification statements as "others" * test: fix InlineInstance tests * DeadCodeEliminations: statements are now als declarations * CheckHighForm: ensure that statement names are not used as references * CheckSpec: throw error if statement name collides * add pass to automatically add missing statement names * check: make sure that two statements cannot have the same name * stmtLabel -> stmtName * scalafmt * add statement names to spec * spec: meta data -> metadata * EnsureStatementNames: explain naming algorithm * remove returns * better namespace use * ir: add CanBeReferenced trait * ir: add newline as jack requested
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-07-31Fixed typo in fixed-point type parameter examples (#1816)Kevin Laeufer
Co-authored-by: chick <chick@qrhino.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-15ir: store FileInfo string in escaped format (#1690)Kevin Laeufer
This should speed up the common case as the compiler never operates on the unescaped string. The new escape function also fixes a bug where ']' was not escaped even though it is the delimiting character for FileInfo. In order to maintain backwards compatibility for the ProtoBuf format, this patch adds escape/unescape calls when going from/to protobuf format. For better performance we should consider changing the protobuf format.
2020-07-13[spec] Specify execution order of side-effect-having statements (#1724)Albert Magyar
* Define 'same clock' in a syntactic sense Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-09[spec] Explicitly disallow shadowing of component names (#1749)Albert Magyar
2020-06-23Basic model checking API (#1653)Tom Alcorn
* Add assume, assert, cover statements * Assert submodule assumptions * Add warning when removing verification statements * Remove System Verilog behaviour emitter warning * Add option to disable AssertSubmoduleAssumptions * Document verification statements in the spec The syntax for the new statements is assert(clk, cond, en, msg) assume(clk, cond, en, msg) cover(clk, cond, en, msg) With assert as a representative example, the semantics is as follows: `clk` is the clock, `cond` is the expression being asserted, `en` is the enable signal (if `en` is low then the assert is not checked) and `msg` is a string message intended to be reported as an error message by the model checker if the assertion fails. In the Verilog emitter, the new statements are handled by a new `formals` map, which groups the statements by clock domain. All model checking statements are then emitted within the context of an `ifdef FORMAL` block, which allows model checking tools (like Symbiyosys) to utilize the statements while keeping them out of synthesis flows. Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-18Fix typo in spec description of 'tail' (#1626)Albert Magyar
* Closes #1597
2020-05-11spec: Ran `aspell` on `spec.tex`. (#1564)Alberto Gonzalez
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-06Update spec.pdfSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-06Clarify spec indentation of when/elseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-06Clarify indentation in specSchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13[spec] Add Fixed to spec (#1456)Albert Magyar
* [spec] Add Fixed to spec * Fixes #1195 * Define type & parameters * Add Fixed as argument type to type conversions * Add Fixed as argument type to relevent PrimOps (with link to tables) * Add asFixed PrimOp * Add IncP/DecP/SetP primops * Add fixed-point width/point propagation tables * Update spec pdf Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-26Update spec to clarify sign and use 'h' for hex throughoutAlbert Magyar
2020-03-13[spec] Update Mid FIRRTL spec to reflect removal of subaccesses (#1451)Albert Magyar
2020-03-02Update single-line when/else example in spec to match implementation (#1414)Albert Magyar
* Closes #890
2020-02-24[spec] clarify that div-by-zero is undefined (#1409)Albert Magyar
2020-02-11[spec] Change sub(UInt, UInt) output type to UInt (#1378)Albert Magyar
2020-02-06Add note to spec about reductions on zero-width wiresAlbert Magyar
2020-01-15improve the tail ir usability. (#1241)Sequencer
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-11-13Add spec for Analog type and attach statement (#1222)Albert Magyar
* Add spec for Analog type and attach statement * Describe role of attaches in partial connection algorithm * Change references that describe ground types where appropriate * Closes #1194 * Fix typo
2019-09-30Define read-write collison for independently clocked mem ports (#1188)Albert Magyar
* Define read-write collison for independently clocked mem ports * Included definition of initiating write/read operation
2019-09-16Update Spec from Gender to FlowSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
* Check mems for legal latencies; ban zero write latency. * Trigger
2019-07-30Make write-under-write section for mems in spec (#1140)Albert Magyar
2019-06-03spec: mixed-input arguments for prim ops are no longer allowed (#1085)Kevin Laeufer
This updates the spec to refelect the changes made in #587. It also fixes issue #968.
2019-03-25Correct a typo in spec.tex (#1063)Felix Yan
2019-01-31Add MidFIRRTL spec (#1003)Albert Magyar
2018-09-27Number all code examples & add specification build to Makefile (#894)Ben Marshall
* Merge makefile changes from dev/specification-fixes - New top level makefile target: `specification` - Builds the specification document. * Number all code examples. This is more a change of convenience than anything. Referring to syntax examples is much easier when they are numbered! This commit is in the context of freechipsproject/firrtl#890 - Updating examples and syntax specification is made easier if they are numbered. - Change `verbatim` environments to `lstlisting` - Add very basic keyword highlighting. - Rebuild specification PDF. On branch dev/number-code-examples Changes to be committed: modified: spec/spec.pdf modified: spec/spec.tex
2018-06-11Fix some typos in leftovers.txt (#822)Felix Yan
2018-03-20Correct extmodule example in spec (#768)Albert Magyar
2018-02-16Update spec for rhsSchuyler Eldridge
Fixes #450 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-12-24Spec erroneously says mod instead of rem.Paul Rigge
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-03Updated future release with stricter low firrtlazidar
2016-09-22Fixed width inference for add, sub (#312)Adam Izraelevitz
Fixes #308 Fixes #193
2016-08-17Change RW port names (#236)Angie Wang
* Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch.
2016-08-16Spec bugfix: update concrete reg syntax example (#233)Adam Izraelevitz
Also added clock to reg's abstract syntax
2016-07-27Merge pull request #205 from ucb-bar/add-future-releaseAdam Izraelevitz
Added future-release.txt
2016-07-27Added future-release.txtazidar
Keeps track of proposed changes to add to the next version of the Firrtl spec.
2016-07-27Fixed reg concrete syntax. #197.azidar
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