diff options
| author | Schuyler Eldridge | 2021-06-30 01:02:36 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2021-06-30 01:02:36 -0400 |
| commit | 9eeeb558553b5d73016c60c2a90d492b84860477 (patch) | |
| tree | 21908e6dd5554614a5dcf9e8c8060187e4deea46 /spec | |
| parent | 5f8ec8b6459d5116e13a832ee3bad8a2fd0eb5ae (diff) | |
Relax spec on 0-bit mux select, use SFC behavior
Change the FIRRTL specification document to allow for 0-bit mux selects.
The existing ZeroWidths pass will promote these to a 1-bit, 0-valued
select signal (which effectively means that the mux can be optimized
away to just the false path).
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Diffstat (limited to 'spec')
| -rw-r--r-- | spec/spec.pdf | bin | 330947 -> 363498 bytes | |||
| -rw-r--r-- | spec/spec.tex | 10 |
2 files changed, 8 insertions, 2 deletions
diff --git a/spec/spec.pdf b/spec/spec.pdf Binary files differindex fcd690e6..d961a28d 100644 --- a/spec/spec.pdf +++ b/spec/spec.pdf diff --git a/spec/spec.tex b/spec/spec.tex index df3422e2..d41d0562 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -1290,7 +1290,7 @@ module MyModule : \subsection{Multiplexers}\label{multiplexers} -A multiplexer outputs one of two input expressions depending on the value of an unsigned single bit selection signal. +A multiplexer outputs one of two input expressions depending on the value of an unsigned selection signal. The following example connects to the \verb|c| port the result of selecting between the \verb|a| and \verb|b| ports. The \verb|a| port is selected when the \verb|sel| signal is high, otherwise the \verb|b| port is selected. \begin{lstlisting} @@ -1304,7 +1304,13 @@ module MyModule : A multiplexer expression is legal only if the following holds. \begin{enumerate} -\item The type of the selection signal is a single bit unsigned integer. +\item The type of the selection signal is an unsigned integer. +\item The width of the selection signal is any of: + \begin{enumerate} + \item Unspecified + \item Zero-bit\footnote{A zero-bit width selection signal will be treated as a one-bit, zero-valued selection signal. \emph{This means that a multiplexer expression with a zero-bit selection signal will always take the false path and will likely be optimized away by a FIRRTL compiler.}} + \item One-bit + \end{enumerate} \item The types of the two input expressions are equivalent. \item The types of the two input expressions are passive (see section \ref{passive_types}). \end{enumerate} |