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AgeCommit message (Expand)Author
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-04-12Fix one hot mux (#573)Chick Markley
2017-04-07Change Enum to emit minimum widths of 1 (#574)Jack Koenig
2017-04-04Use input element to decide if Vec of values has direction (#570)Jack Koenig
2017-04-04Define CompileOptions case class to support CompileOptions manipulation. (#572)Jim Lawson
2017-04-02Make Module instantiations draw clock from Builder instead of parent (#568)Jack Koenig
2017-03-28Creating FixedPoint literals was throwing away width when specifically provided.chick
2017-03-27Support Vec(0) fields in Bundles, just like Option[Data]; add testAndrew Waterman
2017-03-24Fix getWidth on empty Vecs; add testAndrew Waterman
2017-03-24Fixed fix, allow Mux of different binary points and widths (#559)Richard Lin
2017-03-17Add single arg constructor back to compatibility reg (#553)Richard Lin
2017-03-13Revert "Change Vec creation to check if gen is lit (and hence needs t… (#530)Jim Lawson
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-03-08Move log2Up and log2Down to compatibility wrapperAndrew Waterman
2017-03-08Avoid log2Up in testsAndrew Waterman
2017-03-08Avoid log2Up in ShiftRegisterTesterAndrew Waterman
2017-03-08Improve UIntToOH behavior on incorrect inputs; avoid log2UpAndrew Waterman
2017-03-08In OHToUInt, use log2Ceil instead of log2UpAndrew Waterman
2017-03-08Use zero-width wire for 1-entry enumAndrew Waterman
2017-03-08In Counter, use log2Ceil instead of log2UpAndrew Waterman
2017-03-08Fix the widths of QueueIO.count and ArbiterIO.chosen for entries=0Andrew Waterman
2017-03-08Improve Reverse's exception behavior; avoid log2UpAndrew Waterman
2017-03-08Correct Fill's exception behavior; avoid log2UpAndrew Waterman
2017-02-28Use test_run_dir for more tests. (#534)Jim Lawson
2017-02-27Add test for digit field names in RecordsJack Koenig
2017-02-27Update BetterNamingTests to use NamedModuleTesterJack Koenig
2017-02-24Fix mismatch between Chisel and Firrtl on UInt -& UIntJack Koenig
2017-02-24Test that large Vecs can have widths inferredjackkoenig
2017-02-24Escape % in assertion messagesJack Koenig
2017-02-22Bugfix #513. Fix BPSet width inference in Chisel3 (#523)Adam Izraelevitz
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
2017-02-15Implement asTypeOf, refactor internal APIs (#450)Richard Lin
2017-02-15Fixed point factory stuff (#505)Chick Markley
2017-02-08Fix random failures in CompatibilitySpec (#498)Jack Koenig
2017-02-08Add Analog typeJack Koenig
2017-02-08Fix up deprecation warnings and clean up CompatibiltySpec code. (#471)Jim Lawson
2017-02-07Fix up Absolute value #abs (#491)Chick Markley
2017-02-07Add generateFirrtl() method to ChiselSpec.scala (#423)Jim Lawson
2017-02-07Name all the thingsducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
2017-02-03Added vec IO tests for #104 (#480)Jim Lawson
2017-02-02Revamp VendingMachine.scala as cookbook examplejackkoenig
2017-02-02Bring cookbook up to date with chisel3 APIjackkoenig
2017-02-01Move backend compilation utilities (#400)Jim Lawson
2017-01-31Make Module and Bundle properly use empty namespacesJack
2017-01-31Add compile [to Verilog] to ChiselRunnersJack
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
2017-01-30Add shift register with reset (#439)Stevo
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
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