diff options
| author | Andrew Waterman | 2017-02-24 00:31:36 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-03-08 11:27:04 -0600 |
| commit | 94c507b1dab33b7b5f4ca864d6b97cbd1682fc7f (patch) | |
| tree | 2ef7e5e65c1ef6a5205849e1883378439d0239bc /src | |
| parent | 4f81b57bce638815de6671c2652095578773e935 (diff) | |
Avoid log2Up in ShiftRegisterTester
This is an odd one. Using log2Ceil directly results in a Verilator
compile error, presumably due to a FIRRTL zero-width wire bug.
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index e14ec3d9..4dcd6a47 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -97,7 +97,7 @@ class TabulateTester(n: Int) extends BasicTester { class ShiftRegisterTester(n: Int) extends BasicTester { val (cnt, wrap) = Counter(true.B, n*2) - val shifter = Reg(Vec(n, UInt(log2Up(n).W))) + val shifter = Reg(Vec(n, UInt((log2Ceil(n) max 1).W))) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt when (cnt >= n.asUInt) { |