From 94c507b1dab33b7b5f4ca864d6b97cbd1682fc7f Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Fri, 24 Feb 2017 00:31:36 -0800
Subject: Avoid log2Up in ShiftRegisterTester

This is an odd one.  Using log2Ceil directly results in a Verilator
compile error, presumably due to a FIRRTL zero-width wire bug.
---
 src/test/scala/chiselTests/Vec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index e14ec3d9..4dcd6a47 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -97,7 +97,7 @@ class TabulateTester(n: Int) extends BasicTester {
 
 class ShiftRegisterTester(n: Int) extends BasicTester {
   val (cnt, wrap) = Counter(true.B, n*2)
-  val shifter = Reg(Vec(n, UInt(log2Up(n).W)))
+  val shifter = Reg(Vec(n, UInt((log2Ceil(n) max 1).W)))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
   when (cnt >= n.asUInt) {
-- 
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