diff options
| author | Andrew Waterman | 2017-02-24 00:04:43 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-03-08 11:27:04 -0600 |
| commit | 246c2e8336c19d39bfb92dc8f2ee730a2ac4c55b (patch) | |
| tree | 3066a07cd14645c4bbe3ad3f7298aaf6d2a74733 /src | |
| parent | 3e6ef13ff5cda2e65efbbf5d306cc101582ad0e5 (diff) | |
Correct Fill's exception behavior; avoid log2Up
It always should throw an exception when n < 0, but in the specific
case of x.isWidthKnown && x.getWidth == 1, it failed to do so.
This commit also changes log2Up in log2Ceil, which has no effect,
since the argument is always at least 2.
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/util/Bitwise.scala | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index 950fa65f..fec4be9a 100644 --- a/src/main/scala/chisel3/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -65,17 +65,18 @@ object Fill { */ def apply(n: Int, x: UInt): UInt = { n match { + case _ if n < 0 => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.") case 0 => UInt(0.W) case 1 => x case _ if x.isWidthKnown && x.getWidth == 1 => Mux(x.toBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W)) - case _ if n > 1 => - val p2 = Array.ofDim[UInt](log2Up(n + 1)) + case _ => + val nBits = log2Ceil(n + 1) + val p2 = Array.ofDim[UInt](nBits) p2(0) = x for (i <- 1 until p2.length) p2(i) = Cat(p2(i-1), p2(i-1)) - Cat((0 until log2Up(n + 1)).filter(i => (n & (1 << i)) != 0).map(p2(_))) - case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.") + Cat((0 until nBits).filter(i => (n & (1 << i)) != 0).map(p2(_))) } } } |
