diff options
| author | Andrew Waterman | 2017-03-24 15:09:07 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2017-03-24 15:48:36 -0700 |
| commit | e769e5a26f6bd3f87962ad084776c01316ad6fbf (patch) | |
| tree | c21afbc5e3699d531a9df117e2c8ae9ea3a038da /src | |
| parent | 347bd2f9b23eb8cf67089c314741d571adf82aac (diff) | |
Fix getWidth on empty Vecs; add test
Use fold(0) instead of reduce to handle the corner case.
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index d7c2c648..80c4040d 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -134,6 +134,11 @@ class OneBitUnitRegVecTester extends BasicTester { stop() } +class ZeroEntryVecTester extends BasicTester { + require(Vec(0, Bool()).getWidth == 0) + stop() +} + class VecSpec extends ChiselPropSpec { // Disable shrinking on error. implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty) @@ -187,4 +192,8 @@ class VecSpec extends ChiselPropSpec { property("A Reg of a Vec of a single 1 bit element should compile and work") { assertTesterPasses{ new OneBitUnitRegVecTester } } + + property("A Vec with zero entries should compile and have zero width") { + assertTesterPasses{ new ZeroEntryVecTester } + } } |
