1 files changed, 9 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index d7c2c648..80c4040d 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -134,6 +134,11 @@ class OneBitUnitRegVecTester extends BasicTester {
   stop()
 }
 
+class ZeroEntryVecTester extends BasicTester {
+  require(Vec(0, Bool()).getWidth == 0)
+  stop()
+}
+
 class VecSpec extends ChiselPropSpec {
   // Disable shrinking on error.
   implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
@@ -187,4 +192,8 @@ class VecSpec extends ChiselPropSpec {
   property("A Reg of a Vec of a single 1 bit element should compile and work") {
     assertTesterPasses{ new OneBitUnitRegVecTester }
   }
+
+  property("A Vec with zero entries should compile and have zero width") {
+    assertTesterPasses{ new ZeroEntryVecTester }
+  }
 }