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authorchick2017-03-28 00:06:45 -0700
committerchick2017-03-28 00:06:45 -0700
commit19e16642cb99fbb4707ce23fa4df56963e3d39b6 (patch)
treea60cd7d52d596d61eab9ae5bfe3b08c471c8b481 /src
parent8e4ddc62db448b613ae327792e72defca4d115d4 (diff)
Creating FixedPoint literals was throwing away width when specifically provided.
This caused one hot muxing problems in dsptools FixedPoint spec fixed based on error uncovered by this change
Diffstat (limited to 'src')
-rw-r--r--src/test/scala/chiselTests/FixedPointSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/FixedPointSpec.scala b/src/test/scala/chiselTests/FixedPointSpec.scala
index 5047ac62..76a89e6a 100644
--- a/src/test/scala/chiselTests/FixedPointSpec.scala
+++ b/src/test/scala/chiselTests/FixedPointSpec.scala
@@ -79,7 +79,7 @@ class FixedPointFromBitsTester extends BasicTester {
}
class FixedPointMuxTester extends BasicTester {
- val largeWidthLowPrecision = 6.0.F(3.W, 0.BP)
+ val largeWidthLowPrecision = 6.0.F(4.W, 0.BP)
val smallWidthHighPrecision = 0.25.F(2.W, 2.BP)
val unknownWidthLowPrecision = 6.0.F(0.BP)
val unknownFixed = Wire(FixedPoint())