chiselX - Chisel with SFC compatibility

Age	Commit message (Expand)	Author
2017-09-06	Added API to get Verilog from Chisel (#676)	Adam Izraelevitz
2017-08-17	Use firrtl elses in elsewhen/otherwise case emission (#510)	Albert Magyar
2017-08-17	More of the bindings refactor (#635)	Richard Lin
2017-08-17	Make Reset a trait (#672)	Jack Koenig
2017-08-15	Make .dir give correct direction for Module io in compatibility	Jack Koenig
2017-08-11	Rename userDir->specifiedDir (#671)	Richard Lin
2017-08-08	Give default direction to children of Vecs in compatibility code	Jack Koenig
2017-08-07	Don't assign default direction to Analog in Chisel._	Jack Koenig
2017-08-01	Address scalastyle issues, out of date comments, extraneous imports. (#658)	Jim Lawson
2017-07-28	Black box top-level IO fix (#655)	Richard Lin
2017-07-28	Add rebinding test (#654)	Richard Lin
2017-07-27	Fix style of literal creators (#637)	Chick Markley
2017-07-07	Ensure IO is non-null before attempting to autoWrapPorts. (#643)	Jim Lawson
2017-06-26	Directions internals mega-refactor (#617)	Richard Lin
2017-05-31	Add dontTouch for annotating Data to not be removed	Jack Koenig
2017-05-31	Dont try to instantiate firrtl.Transform from Annotation	Jack Koenig
2017-05-28	Correct misleading example code	Edward Wang
2017-05-25	Support updated scalatest/scalacheck; bump sbt and Scala versions. (#605)	Jim Lawson
2017-05-25	Update internal Pipe wiring - fixes #615" (#616)	Jim Lawson
2017-05-19	Update comments describing Decoupled/ReadyValid - fix #437. (#493)	Jim Lawson
2017-05-11	Scope resources - move them down into chisel3 directory - fixes #549 (#610)	Jim Lawson
2017-05-10	Add implicit CompileOptions to Record and Bundle (#595)	Jack Koenig
2017-05-04	Connecting basic types wrong should error in chisel (#497)	Chick Markley
2017-05-03	Clear clock and reset scope for RawModule (#607)	Richard Lin
2017-04-26	Deprecate fromBits and clock/reset constructors (#583)	Richard Lin
2017-04-26	Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)	Jim Lawson
2017-04-25	Remove explicit import of NotStrict - fixes #492 (#494)	Jim Lawson
2017-04-15	Fix assignment from 0-entry Vec: add test (#580)	Andrew Waterman
2017-04-13	Module Hierarchy Refactor (#469)	Richard Lin
2017-04-12	Fix one hot mux (#573)	Chick Markley
2017-04-07	Change Enum to emit minimum widths of 1 (#574)	Jack Koenig
2017-04-04	Use input element to decide if Vec of values has direction (#570)	Jack Koenig
2017-04-04	Define CompileOptions case class to support CompileOptions manipulation. (#572)	Jim Lawson
2017-04-02	Make Module instantiations draw clock from Builder instead of parent (#568)	Jack Koenig
2017-03-28	Creating FixedPoint literals was throwing away width when specifically provided.	chick
2017-03-27	Support Vec(0) fields in Bundles, just like Option[Data]; add test	Andrew Waterman
2017-03-24	Fix getWidth on empty Vecs; add test	Andrew Waterman
2017-03-24	Fixed fix, allow Mux of different binary points and widths (#559)	Richard Lin
2017-03-17	Add single arg constructor back to compatibility reg (#553)	Richard Lin
2017-03-13	Revert "Change Vec creation to check if gen is lit (and hence needs t… (#530)	Jim Lawson
2017-03-08	Deprecate old Reg with nulls constructor (#455)	Richard Lin
2017-03-08	Move log2Up and log2Down to compatibility wrapper	Andrew Waterman
2017-03-08	Avoid log2Up in tests	Andrew Waterman
2017-03-08	Avoid log2Up in ShiftRegisterTester	Andrew Waterman
2017-03-08	Improve UIntToOH behavior on incorrect inputs; avoid log2Up	Andrew Waterman
2017-03-08	In OHToUInt, use log2Ceil instead of log2Up	Andrew Waterman
2017-03-08	Use zero-width wire for 1-entry enum	Andrew Waterman
2017-03-08	In Counter, use log2Ceil instead of log2Up	Andrew Waterman
2017-03-08	Fix the widths of QueueIO.count and ArbiterIO.chosen for entries=0	Andrew Waterman
2017-03-08	Improve Reverse's exception behavior; avoid log2Up	Andrew Waterman