summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2017-09-14Update sbt to 0.13.16; add Scala 2.12 support. (#675)Jim Lawson
2017-09-06Added API to get Verilog from Chisel (#676)Adam Izraelevitz
2017-08-28typo in READMEMartin Schoeberl
2017-08-28Another try of a smoother intro what Chisel isMartin Schoeberl
2017-08-17Use firrtl elses in elsewhen/otherwise case emission (#510)Albert Magyar
2017-08-17More of the bindings refactor (#635)Richard Lin
2017-08-17Make Reset a trait (#672)Jack Koenig
2017-08-15Make .dir give correct direction for Module io in compatibilityJack Koenig
2017-08-11Rename userDir->specifiedDir (#671)Richard Lin
2017-08-11README: Java packageMartin Schoeberl
2017-08-08Give default direction to children of Vecs in compatibility codeJack Koenig
2017-08-07Don't assign default direction to Analog in Chisel._Jack Koenig
2017-08-02Disable aggregation until we can apply it selectively (#660)Jim Lawson
2017-08-01Update Makefile, build.sbt to support subproject coverage (#659)Jim Lawson
2017-08-01Address scalastyle issues, out of date comments, extraneous imports. (#658)Jim Lawson
2017-07-28Black box top-level IO fix (#655)Richard Lin
2017-07-28Add rebinding test (#654)Richard Lin
2017-07-27Fix style of literal creators (#637)Chick Markley
2017-07-25Simplify macOS install instructionsyep
2017-07-25Fixed point width inference was wrong when binary points didn't align. (#590)Angie Wang
2017-07-17Update deprecated code in build.sbt (#648)Jim Lawson
2017-07-07Ensure IO is non-null before attempting to autoWrapPorts. (#643)Jim Lawson
2017-07-06Fix syntax of README.md (#641)Michael Gielda
2017-06-26Directions internals mega-refactor (#617)Richard Lin
2017-06-19Fix a small typo in the READMEAnders Pitman
2017-05-31Add dontTouch for annotating Data to not be removedJack Koenig
2017-05-31Dont try to instantiate firrtl.Transform from AnnotationJack Koenig
2017-05-28Correct misleading example codeEdward Wang
2017-05-25Support updated scalatest/scalacheck; bump sbt and Scala versions. (#605)Jim Lawson
2017-05-25Update internal Pipe wiring - fixes #615" (#616)Jim Lawson
2017-05-19Update comments describing Decoupled/ReadyValid - fix #437. (#493)Jim Lawson
2017-05-12Changed multiplication of SInt and UInt (#611)Adam Izraelevitz
2017-05-11Scope resources - move them down into chisel3 directory - fixes #549 (#610)Jim Lawson
2017-05-10Add implicit CompileOptions to Record and Bundle (#595)Jack Koenig
2017-05-04Connecting basic types wrong should error in chisel (#497)Chick Markley
2017-05-03Clear clock and reset scope for RawModule (#607)Richard Lin
2017-04-27Update instructions for installing firrtl. (#597)Jim Lawson
2017-04-26Deprecate fromBits and clock/reset constructors (#583)Richard Lin
2017-04-26Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)Jim Lawson
2017-04-25Remove explicit import of NotStrict - fixes #492 (#494)Jim Lawson
2017-04-21Remove VecLike/IndexedSeq from Mem type (#589)Richard Lin
2017-04-15 Fix assignment from 0-entry Vec: add test (#580)Andrew Waterman
2017-04-14Fix macOS install instructions for homebrew package manager (#575)yep
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-04-12Fix one hot mux (#573)Chick Markley
2017-04-07Change Enum to emit minimum widths of 1 (#574)Jack Koenig
2017-04-04Use input element to decide if Vec of values has direction (#570)Jack Koenig
2017-04-04Define CompileOptions case class to support CompileOptions manipulation. (#572)Jim Lawson
2017-04-02Make Module instantiations draw clock from Builder instead of parent (#568)Jack Koenig
2017-04-02Merge pull request #564 from ucb-bar/bugfix-lost-width-on-fixed-literalsgrebe
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 14:12:01 +0000