Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)

* Remove explicit import of NotStrict - fixes #492

* Provide macro for MemBase.apply().

* Provide macro for MemBase.apply().
Since a macro cannot override an abstract method, provide a concrete
apply method n VecLike() that we can override with a macro.

* Remove concrete apply() in VecLike.
Since MemBase no longer extends the trait VecLike, we do not require a concrete method to which we can apply a macro to extract the appropriate CompileOptions.

* Add missing implicit compileOptions to do_pad() and do_zext().
The latter caused:
```
[error] /vm/home/jenkins/workspace/rocket-chip_with_chisel3/hardfloat/src/main/scala/MulAddRecFN.scala:205: too many arguments for method do_zext: (implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo)chisel3.core.SInt
[error]     val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
```

* Add SourceInfoTransform macros to Vec methods in order to avoid apply() chain issues.
Since utils methods are no longer NotStrict, Pipe objects need access to the client's compile options. There may be more.

* Respond to review comments.
Don't propagate SourceInfo through helper functions.
Replace old usages of CompileOptionsTransform with the now equivalent SourceInfoTransform and redefine CompileOptionsTransform to only deal with CompileOptions.
Just thread CompileOptions (not SourceInfo) through deprecated functions.

6 files changed, 27 insertions, 22 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 97028995..6a4d8cff 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -223,10 +223,12 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
 
   /** Creates a dynamically indexed read or write accessor into the array.
     */
-  def apply(idx: UInt)(implicit compileOptions: CompileOptions): T = {
-    Binding.checkSynthesizable(idx ,s"'idx' ($idx)")
+  override def apply(p: UInt): T = macro CompileOptionsTransform.pArg
+
+  def do_apply(p: UInt)(implicit compileOptions: CompileOptions): T = {
+    Binding.checkSynthesizable(p ,s"'p' ($p)")
     val port = gen
-    val i = Vec.truncateIndex(idx, length)(UnlocatableSourceInfo, compileOptions)
+    val i = Vec.truncateIndex(p, length)(UnlocatableSourceInfo, compileOptions)
     port.setRef(this, i)
 
     // Bind each element of port to being whatever the base type is
@@ -243,11 +245,11 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
   def apply(idx: Int): T = self(idx)
 
   @deprecated("Use Vec.apply instead", "chisel3")
-  def read(idx: UInt)(implicit compileOptions: CompileOptions): T = apply(idx)
+  def read(idx: UInt)(implicit compileOptions: CompileOptions): T = do_apply(idx)(compileOptions)
 
   @deprecated("Use Vec.apply instead", "chisel3")
   def write(idx: UInt, data: T)(implicit compileOptions: CompileOptions): Unit = {
-    apply(idx)(compileOptions).:=(data)(DeprecatedSourceInfo, compileOptions)
+    do_apply(idx)(compileOptions).:=(data)(DeprecatedSourceInfo, compileOptions)
   }
 
   override def cloneType: this.type = {
@@ -277,7 +279,9 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
   * operations.
   */
 trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
-  def apply(idx: UInt)(implicit compileOptions: CompileOptions): T
+  def apply(p: UInt): T = macro CompileOptionsTransform.pArg
+
+  def do_apply(p: UInt)(implicit compileOptions: CompileOptions): T
 
   // IndexedSeq has its own hashCode/equals that we must not use
   override def hashCode: Int = super[HasId].hashCode
@@ -325,14 +329,14 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
 
   /** Outputs the index of the first element for which p outputs true.
     */
-  def indexWhere(p: T => Bool): UInt = macro CompileOptionsTransform.pArg
+  def indexWhere(p: T => Bool): UInt = macro SourceInfoTransform.pArg
 
   def do_indexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
     SeqUtils.priorityMux(indexWhereHelper(p))
 
   /** Outputs the index of the last element for which p outputs true.
     */
-  def lastIndexWhere(p: T => Bool): UInt = macro CompileOptionsTransform.pArg
+  def lastIndexWhere(p: T => Bool): UInt = macro SourceInfoTransform.pArg
 
   def do_lastIndexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
     SeqUtils.priorityMux(indexWhereHelper(p).reverse)
@@ -347,7 +351,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
     * true is NOT checked (useful in cases where the condition doesn't always
     * hold, but the results are not used in those cases)
     */
-  def onlyIndexWhere(p: T => Bool): UInt = macro CompileOptionsTransform.pArg
+  def onlyIndexWhere(p: T => Bool): UInt = macro SourceInfoTransform.pArg
 
   def do_onlyIndexWhere(p: T => Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
     SeqUtils.oneHotMux(indexWhereHelper(p))
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index f18fb541..e8423a99 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -178,7 +178,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
     */
   final def pad(that: Int): this.type = macro SourceInfoTransform.thatArg
 
-  def do_pad(that: Int)(implicit sourceInfo: SourceInfo): this.type =
+  def do_pad(that: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): this.type =
     binop(sourceInfo, cloneTypeWidth(this.width max Width(that)), PadOp, that)
 
   /** Returns this wire bitwise-inverted. */
@@ -509,7 +509,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   // TODO: this eventually will be renamed as toSInt, once the existing toSInt
   // completes its deprecation phase.
   final def zext(): SInt = macro SourceInfoTransform.noArg
-  def do_zext(implicit sourceInfo: SourceInfo): SInt =
+  def do_zext(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt =
     pushOp(DefPrim(sourceInfo, SInt(width + 1), ConvertOp, ref))
 
   /** Returns this UInt as a [[SInt]], without changing width or bit value. The
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 30e1bf97..e945cfbe 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -314,7 +314,7 @@ abstract class Data extends HasId {
     * @note bit widths are NOT checked, may pad or drop bits from input
     * @note that should have known widths
     */
-  def asTypeOf[T <: Data](that: T): T = macro CompileOptionsTransform.thatArg
+  def asTypeOf[T <: Data](that: T): T = macro SourceInfoTransform.thatArg
 
   def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
     val thatCloned = Wire(that.chiselCloneType)
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index db3928e3..49e96ddf 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -40,7 +40,7 @@ private[chisel3] object SeqUtils {
 
   /** Returns the data value corresponding to the first true predicate.
     */
-  def priorityMux[T <: Data](in: Seq[(Bool, T)]): T = macro CompileOptionsTransform.inArg
+  def priorityMux[T <: Data](in: Seq[(Bool, T)]): T = macro SourceInfoTransform.inArg
 
   def do_priorityMux[T <: Data](in: Seq[(Bool, T)])
                                (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
@@ -57,7 +57,7 @@ private[chisel3] object SeqUtils {
     * @note assumes exactly one true predicate, results undefined otherwise
     *       FixedPoint values or aggregates containing FixedPoint values cause this optimized structure to be lost
     */
-  def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = macro CompileOptionsTransform.inArg
+  def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = macro SourceInfoTransform.inArg
 
   //scalastyle:off method.length cyclomatic.complexity
   def do_oneHotMux[T <: Data](in: Iterable[(Bool, T)])
diff --git a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
index 01d133de..b7d40901 100644
--- a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
@@ -129,15 +129,15 @@ class CompileOptionsTransform(val c: Context) extends AutoSourceTransform {
   import c.universe._
 
   def thatArg(that: c.Tree): c.Tree = {
-    q"$thisObj.$doFuncTerm($that)($implicitSourceInfo, $implicitCompileOptions)"
+    q"$thisObj.$doFuncTerm($that)($implicitCompileOptions)"
   }
 
   def inArg(in: c.Tree): c.Tree = {
-    q"$thisObj.$doFuncTerm($in)($implicitSourceInfo, $implicitCompileOptions)"
+    q"$thisObj.$doFuncTerm($in)($implicitCompileOptions)"
   }
 
   def pArg(p: c.Tree): c.Tree = {
-    q"$thisObj.$doFuncTerm($p)($implicitSourceInfo, $implicitCompileOptions)"
+    q"$thisObj.$doFuncTerm($p)($implicitCompileOptions)"
   }
 }
 
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 8182c475..f95bb17c 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -6,6 +6,7 @@
 package chisel3.util
 
 import chisel3._
+import chisel3.core.CompileOptions
 import chisel3.internal.naming.chiselName  // can't use chisel3_ version because of compile order
 
 /** An Bundle containing data and a signal determining if it is valid */
@@ -34,7 +35,7 @@ object Valid {
 object Pipe
 {
   @chiselName
-  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): Valid[T] = {
+  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = {
     if (latency == 0) {
       val out = Wire(Valid(enqBits))
       out.valid <> enqValid
@@ -43,14 +44,14 @@ object Pipe
     } else {
       val v = RegNext(enqValid, false.B)
       val b = RegEnable(enqBits, enqValid)
-      apply(v, b, latency-1)
+      apply(v, b, latency-1)(compileOptions)
     }
   }
-  def apply[T <: Data](enqValid: Bool, enqBits: T): Valid[T] = apply(enqValid, enqBits, 1)
-  def apply[T <: Data](enq: Valid[T], latency: Int = 1): Valid[T] = apply(enq.valid, enq.bits, latency)
+  def apply[T <: Data](enqValid: Bool, enqBits: T)(implicit compileOptions: CompileOptions): Valid[T] = apply(enqValid, enqBits, 1)(compileOptions)
+  def apply[T <: Data](enq: Valid[T], latency: Int = 1)(implicit compileOptions: CompileOptions): Valid[T] = apply(enq.valid, enq.bits, latency)(compileOptions)
 }
 
-class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module
+class Pipe[T <: Data](gen: T, latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module
 {
   class PipeIO extends Bundle {
     val enq = Input(Valid(gen))