diff options
| author | Jack Koenig | 2017-08-07 16:19:10 -0700 |
|---|---|---|
| committer | Jack Koenig | 2017-08-08 10:30:54 -0700 |
| commit | 5b6802e8f231805f638f8fe057bee342a56a78e7 (patch) | |
| tree | bec698065d234e94e1264b150de039f5cac6c071 | |
| parent | 156435b80e32175883be21c7ab53784dd94f5c53 (diff) | |
Give default direction to children of Vecs in compatibility code
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 8 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/CompatibilitySpec.scala | 11 |
2 files changed, 16 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 0f081daf..558e6432 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -235,9 +235,11 @@ abstract class BaseModule extends HasId { case data: Aggregate => data.userDirection match { // Recurse into children to ensure explicit direction set somewhere case UserDirection.Unspecified | UserDirection.Flip => data match { - case data: Record if (!data.compileOptions.dontAssumeDirectionality) => - data.getElements.foreach(assignCompatDir(_, true)) - case _ => data.getElements.foreach(assignCompatDir(_, false)) + case record: Record => + val compatRecord = !record.compileOptions.dontAssumeDirectionality + record.getElements.foreach(assignCompatDir(_, compatRecord)) + case vec: Vec[_] => + vec.getElements.foreach(assignCompatDir(_, insideCompat)) } case UserDirection.Input | UserDirection.Output => // forced assign, nothing to do } diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index f3934f76..abbc040a 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -249,4 +249,15 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks } elaborate { new DirectionLessConnectionModule() } } + + "Vec ports" should "give default directions to children so they can be used in chisel3.util" in { + import Chisel._ + elaborate(new Module { + val io = new Bundle { + val in = Vec(1, UInt(width = 8)).flip + val out = UInt(width = 8) + } + io.out := RegEnable(io.in(0), true.B) + }) + } } |
