Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)

* Remove explicit import of NotStrict - fixes #492

* Provide macro for MemBase.apply().

* Provide macro for MemBase.apply().
Since a macro cannot override an abstract method, provide a concrete
apply method n VecLike() that we can override with a macro.

* Remove concrete apply() in VecLike.
Since MemBase no longer extends the trait VecLike, we do not require a concrete method to which we can apply a macro to extract the appropriate CompileOptions.

* Add missing implicit compileOptions to do_pad() and do_zext().
The latter caused:
```
[error] /vm/home/jenkins/workspace/rocket-chip_with_chisel3/hardfloat/src/main/scala/MulAddRecFN.scala:205: too many arguments for method do_zext: (implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo)chisel3.core.SInt
[error]     val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
```

* Add SourceInfoTransform macros to Vec methods in order to avoid apply() chain issues.
Since utils methods are no longer NotStrict, Pipe objects need access to the client's compile options. There may be more.

* Respond to review comments.
Don't propagate SourceInfo through helper functions.
Replace old usages of CompileOptionsTransform with the now equivalent SourceInfoTransform and redefine CompileOptionsTransform to only deal with CompileOptions.
Just thread CompileOptions (not SourceInfo) through deprecated functions.

1 files changed, 6 insertions, 5 deletions

diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 8182c475..f95bb17c 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -6,6 +6,7 @@
 package chisel3.util
 
 import chisel3._
+import chisel3.core.CompileOptions
 import chisel3.internal.naming.chiselName  // can't use chisel3_ version because of compile order
 
 /** An Bundle containing data and a signal determining if it is valid */
@@ -34,7 +35,7 @@ object Valid {
 object Pipe
 {
   @chiselName
-  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): Valid[T] = {
+  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = {
     if (latency == 0) {
       val out = Wire(Valid(enqBits))
       out.valid <> enqValid
@@ -43,14 +44,14 @@ object Pipe
     } else {
       val v = RegNext(enqValid, false.B)
       val b = RegEnable(enqBits, enqValid)
-      apply(v, b, latency-1)
+      apply(v, b, latency-1)(compileOptions)
     }
   }
-  def apply[T <: Data](enqValid: Bool, enqBits: T): Valid[T] = apply(enqValid, enqBits, 1)
-  def apply[T <: Data](enq: Valid[T], latency: Int = 1): Valid[T] = apply(enq.valid, enq.bits, latency)
+  def apply[T <: Data](enqValid: Bool, enqBits: T)(implicit compileOptions: CompileOptions): Valid[T] = apply(enqValid, enqBits, 1)(compileOptions)
+  def apply[T <: Data](enq: Valid[T], latency: Int = 1)(implicit compileOptions: CompileOptions): Valid[T] = apply(enq.valid, enq.bits, latency)(compileOptions)
 }
 
-class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module
+class Pipe[T <: Data](gen: T, latency: Int = 1)(implicit compileOptions: CompileOptions) extends Module
 {
   class PipeIO extends Bundle {
     val enq = Input(Valid(gen))