chiselX - Chisel with SFC compatibility

Age	Commit message (Expand)	Author
2022-09-01	Remove incorrect clock warning on Mem.read (backport #2721) (#2722)	mergify[bot]
2022-02-01	Optional clock param for memory ports (#2333) (#2382)	mergify[bot]
2022-01-10	Apply scalafmt	Jack Koenig
2020-10-01	Move Chisel3 to SPDX license conventions (#1604)	Chick Markley
2020-06-29	- A few final fixes after the rebase	chick
2020-06-29	This adds a mechanism for the unittests to be run with the TreadleBackend	chick
2020-06-22	Use ChiselStage in Tests	Schuyler Eldridge
2019-02-19	Mainline Chisel multi-clock functionality (#1013)	edwardcwang
2019-01-25	WireDefault instead of WireInit, keep WireInit around (#986)	Martin Schoeberl
2018-12-04	Add asBool, deprecate toBool	Jack Koenig
2018-06-01	Literals set their ref so they no longer get named (#826)	Jack Koenig
2017-08-17	More of the bindings refactor (#635)	Richard Lin
2017-08-17	Make Reset a trait (#672)	Jack Koenig
2017-04-02	Make Module instantiations draw clock from Builder instead of parent (#568)	Jack Koenig
2017-03-08	Deprecate old Reg with nulls constructor (#455)	Richard Lin
2017-02-16	Add support for clock and reset scoping (#509)	Jack Koenig