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authoredwardcwang2019-02-19 16:14:39 -0800
committerSchuyler Eldridge2019-02-19 19:14:39 -0500
commit4c512593fb5688f3de502ba1ed70681a0802b6c9 (patch)
treed4aab14f0bdf523a24591ee2ed90e83014fe07c6 /src/test/scala/chiselTests/MultiClockSpec.scala
parente4ddef0c0b202190c913e130481819dc5ce48d7a (diff)
Mainline Chisel multi-clock functionality (#1013)
Close #1009
Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
-rw-r--r--src/test/scala/chiselTests/MultiClockSpec.scala1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 6e84c9b2..770a9e9a 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -3,7 +3,6 @@
package chiselTests
import chisel3._
-import chisel3.experimental.{withClockAndReset, withClock, withReset}
import chisel3.util.Counter
import chisel3.testers.BasicTester