diff options
| author | Richard Lin | 2017-08-17 17:24:02 -0700 |
|---|---|---|
| committer | Jack Koenig | 2017-08-17 17:24:02 -0700 |
| commit | 6e12ed9fd7a771eb30f44b8e1c4ab33f6ad8e0a6 (patch) | |
| tree | 0ff452193d515adc32ecccacb2b58daa9a1d95cb /src/test/scala/chiselTests/MultiClockSpec.scala | |
| parent | 802cfc4405c28ae212a955a92c7a6ad2d2b6f0c2 (diff) | |
More of the bindings refactor (#635)
Rest of the binding refactor
Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 3f9ad895..7886649f 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -54,7 +54,7 @@ class MultiClockSubModuleTest extends BasicTester { /** Test withReset changing the reset of a Reg */ class WithResetTest extends BasicTester { - val reset2 = Wire(init = false.B) + val reset2 = WireInit(false.B) val reg = withReset(reset2 || reset.toBool) { RegInit(0.U(8.W)) } reg := reg + 1.U |