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| author | Jack Koenig | 2017-08-17 11:26:29 -0700 |
|---|---|---|
| committer | GitHub | 2017-08-17 11:26:29 -0700 |
| commit | 802cfc4405c28ae212a955a92c7a6ad2d2b6f0c2 (patch) | |
| tree | 23f8d8be14506cb2cfcacfd89eb4ef35cccfe925 /src/test/scala/chiselTests/MultiClockSpec.scala | |
| parent | 90e775b1228765ce7f345716fa215f72b97816a9 (diff) | |
Make Reset a trait (#672)
Bool implements Reset. Compatibility package includes an implicit
conversion from Reset to Bool.
Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index ada0b9b0..3f9ad895 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -55,7 +55,7 @@ class MultiClockSubModuleTest extends BasicTester { /** Test withReset changing the reset of a Reg */ class WithResetTest extends BasicTester { val reset2 = Wire(init = false.B) - val reg = withReset(reset2 || reset) { RegInit(0.U(8.W)) } + val reg = withReset(reset2 || reset.toBool) { RegInit(0.U(8.W)) } reg := reg + 1.U val (cycle, done) = Counter(true.B, 10) |