Make Reset a trait (#672)

Bool implements Reset. Compatibility package includes an implicit
conversion from Reset to Bool.

4 files changed, 37 insertions, 16 deletions

diff --git a/src/test/scala/chiselTests/FromBitsTester.scala b/src/test/scala/chiselTests/AsTypeOfTester.scala
index e916272f..75a2dc8a 100644
--- a/src/test/scala/chiselTests/FromBitsTester.scala
+++ b/src/test/scala/chiselTests/AsTypeOfTester.scala
@@ -9,7 +9,7 @@ import chisel3.experimental.{DataMirror, FixedPoint}
 import chisel3.testers.BasicTester
 import chisel3.util._
 
-class FromBitsBundleTester extends BasicTester {
+class AsTypeOfBundleTester extends BasicTester {
   class MultiTypeBundle extends Bundle {
     val u  = UInt(4.W)
     val s  = SInt(4.W)
@@ -18,16 +18,16 @@ class FromBitsBundleTester extends BasicTester {
 
   val bun = new MultiTypeBundle
 
-  val bunFromBits = ((4 << 8) + (15 << 4) + (12 << 0)).U.asTypeOf(bun)
+  val bunAsTypeOf = ((4 << 8) + (15 << 4) + (12 << 0)).U.asTypeOf(bun)
 
-  assert(bunFromBits.u === 4.U)
-  assert(bunFromBits.s === -1.S)
-  assert(bunFromBits.fp === FixedPoint.fromDouble(-0.5, 4.W, 3.BP))
+  assert(bunAsTypeOf.u === 4.U)
+  assert(bunAsTypeOf.s === -1.S)
+  assert(bunAsTypeOf.fp === FixedPoint.fromDouble(-0.5, 4.W, 3.BP))
 
   stop()
 }
 
-class FromBitsVecTester extends BasicTester {
+class AsTypeOfVecTester extends BasicTester {
   val vec = ((15 << 12) + (0 << 8) + (1 << 4) + (2 << 0)).U.asTypeOf(Vec(4, SInt(4.W)))
 
   assert(vec(0) === 2.S)
@@ -38,7 +38,7 @@ class FromBitsVecTester extends BasicTester {
   stop()
 }
 
-class FromBitsTruncationTester extends BasicTester {
+class AsTypeOfTruncationTester extends BasicTester {
   val truncate = (64 + 3).U.asTypeOf(UInt(3.W))
   val expand   = 1.U.asTypeOf(UInt(3.W))
 
@@ -50,18 +50,27 @@ class FromBitsTruncationTester extends BasicTester {
   stop()
 }
 
-class FromBitsSpec extends ChiselFlatSpec {
-  behavior of "fromBits"
+class ResetAsTypeOfBoolTester extends BasicTester {
+  assert(reset.asTypeOf(Bool()) === reset.toBool)
+  stop()
+}
+
+class AsTypeOfSpec extends ChiselFlatSpec {
+  behavior of "asTypeOf"
 
   it should "work with Bundles containing Bits Types" in {
-    assertTesterPasses{ new FromBitsBundleTester }
+    assertTesterPasses{ new AsTypeOfBundleTester }
   }
 
   it should "work with Vecs containing Bits Types" in {
-    assertTesterPasses{ new FromBitsVecTester }
+    assertTesterPasses{ new AsTypeOfVecTester }
   }
 
   it should "expand and truncate UInts of different width" in {
-    assertTesterPasses{ new FromBitsTruncationTester }
+    assertTesterPasses{ new AsTypeOfTruncationTester }
+  }
+
+  it should "work for casting implicit Reset to Bool" in {
+    assertTesterPasses{ new ResetAsTypeOfBoolTester  }
   }
 }
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 92559123..994a16fd 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -10,7 +10,7 @@ import chisel3.util._
 class FailingAssertTester() extends BasicTester {
   assert(false.B)
   // Wait to come out of reset
-  val (_, done) = Counter(!reset, 4)
+  val (_, done) = Counter(!reset.toBool, 4)
   when (done) {
     stop()
   }
@@ -19,7 +19,7 @@ class FailingAssertTester() extends BasicTester {
 class SucceedingAssertTester() extends BasicTester {
   assert(true.B)
   // Wait to come out of reset
-  val (_, done) = Counter(!reset, 4)
+  val (_, done) = Counter(!reset.toBool, 4)
   when (done) {
     stop()
   }
@@ -38,7 +38,7 @@ class PipelinedResetTester extends BasicTester {
 
   module.reset := RegNext(RegNext(RegNext(reset)))
 
-  val (_, done) = Counter(!reset, 4)
+  val (_, done) = Counter(!reset.toBool, 4)
   when (done) {
     stop()
   }
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 52a93aed..7feee96f 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -270,6 +270,17 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
     })
   }
 
+  "Reset" should "still walk, talk, and quack like a Bool" in {
+    import Chisel._
+    elaborate(new Module {
+      val io = new Bundle {
+        val in = Bool(INPUT)
+        val out = Bool(OUTPUT)
+      }
+      io.out := io.in && reset
+    })
+  }
+
   "Data.dir" should "give the correct direction for io" in {
     import Chisel._
     elaborate(new Module {
@@ -292,4 +303,5 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
       })
     }
   }
+
 }
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index ada0b9b0..3f9ad895 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -55,7 +55,7 @@ class MultiClockSubModuleTest extends BasicTester {
 /** Test withReset changing the reset of a Reg */
 class WithResetTest extends BasicTester {
   val reset2 = Wire(init = false.B)
-  val reg = withReset(reset2 || reset) { RegInit(0.U(8.W)) }
+  val reg = withReset(reset2 || reset.toBool) { RegInit(0.U(8.W)) }
   reg := reg + 1.U
 
   val (cycle, done) = Counter(true.B, 10)