diff options
| author | chick | 2019-12-17 13:26:08 -0800 |
|---|---|---|
| committer | chick | 2020-06-29 10:22:11 -0700 |
| commit | 0a17d89fe76c11efadc3d0f90dc1d93a690d861a (patch) | |
| tree | a4cfb7c210767a315473014ecd600e9857d1799f /src/test/scala/chiselTests/MultiClockSpec.scala | |
| parent | a1edc8f4cd525c8475e847ff7ddd9cb8fc1d3c51 (diff) | |
This adds a mechanism for the unittests to be run with the TreadleBackend
This mechanism is not enabled and should not change the behavior of existing tests
A following PR will deliver a switch that will allow changing the backend.
The reasons for this PR
- Treadle tests run much faster, enabling quicker debugging and CI cycles
- This will help ensure fidelity of Treadle to the Verilator backend
A few tests are marked as verilator only due to black box limitations
Change treadle to a direct dependency
I tried to make it a test only dependency but the TesterDriver sits in src/main requiring that
regular compile have access to treadle
Oops, made treadle the default
A number of changes in response to @ducky64 review
- made backend check clearer and add error handling for multiple backends specified
- Fixed duplicate TargetDirAnnotation uses in Treadle backend
- Cleaned up BlackBox test formatting
- Undid unnecessary debugging changes from Counter
- Undid .gitignore change, that should be on another PR
A number of changes in response to @ducky64 review
- Undid debugging changes made to BitWiseOps
Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 1a71570d..8b7fddb0 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -120,7 +120,7 @@ class MultiClockSpec extends ChiselFlatSpec { } it should "scope ports of memories" in { - assertTesterPasses(new MultiClockMemTest) + assertTesterPasses(new MultiClockMemTest, annotations = TesterDriver.verilatorOnly) } it should "return like a normal Scala block" in { |
