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Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 1a71570d..8b7fddb0 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -120,7 +120,7 @@ class MultiClockSpec extends ChiselFlatSpec { } it should "scope ports of memories" in { - assertTesterPasses(new MultiClockMemTest) + assertTesterPasses(new MultiClockMemTest, annotations = TesterDriver.verilatorOnly) } it should "return like a normal Scala block" in { |