diff options
| author | chick | 2020-06-29 10:44:13 -0700 |
|---|---|---|
| committer | chick | 2020-06-29 10:44:13 -0700 |
| commit | 3694b092830ac0a8d1e5a6dfe9a65d88420c1962 (patch) | |
| tree | b13d75011859e3adf806f3747c542daa9662fba1 /src/test/scala/chiselTests/MultiClockSpec.scala | |
| parent | 0a17d89fe76c11efadc3d0f90dc1d93a690d861a (diff) | |
- A few final fixes after the rebase
Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 8b7fddb0..0b9497b8 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -4,7 +4,7 @@ package chiselTests import chisel3._ import chisel3.util.Counter -import chisel3.testers.BasicTester +import chisel3.testers.{BasicTester, TesterDriver} import chisel3.stage.ChiselStage /** Multi-clock test of a Reg using a different clock via withClock */ |