From 3694b092830ac0a8d1e5a6dfe9a65d88420c1962 Mon Sep 17 00:00:00 2001
From: chick
Date: Mon, 29 Jun 2020 10:44:13 -0700
Subject: - A few final fixes after the rebase

---
 src/test/scala/chiselTests/MultiClockSpec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')

diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 8b7fddb0..0b9497b8 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util.Counter
-import chisel3.testers.BasicTester
+import chisel3.testers.{BasicTester, TesterDriver}
 import chisel3.stage.ChiselStage
 
 /** Multi-clock test of a Reg using a different clock via withClock */
-- 
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