- A few final fixes after the rebase

6 files changed, 19 insertions, 20 deletions

diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index e63e86e7..6231f81a 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -5,17 +5,11 @@ package chisel3.testers
 import java.io._
 
 import chisel3._
-import chisel3.experimental.RunFirrtlTransform
-import chisel3.stage.phases.{AspectPhase, Convert, Elaborate, Emitter}
-import chisel3.stage.{
-  ChiselCircuitAnnotation,
-  ChiselGeneratorAnnotation,
-  ChiselOutputFileAnnotation,
-  ChiselStage,
-  DesignAnnotation
-}
-import firrtl.{Driver => _, _}
-import firrtl.options.{Dependency, Phase, PhaseManager}
+import chisel3.stage.phases.{Convert, Elaborate, Emitter}
+import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, ChiselStage, NoRunFirrtlCompilerAnnotation}
+import firrtl.AnnotationSeq
+import firrtl.annotations.NoTargetAnnotation
+import firrtl.options.{Dependency, Phase, PhaseManager, TargetDirAnnotation, Unserializable}
 import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage}
 import firrtl.transforms.BlackBoxSourceHelper.writeResourceToDirectory
 import treadle.executable.StopException
@@ -33,7 +27,8 @@ object TesterDriver extends BackendCompilationUtilities {
 
   /*
   Currently the only mechanism for running with the Treadle backend is to edit this
-  statement locally.
+  statement locally. To:
+  `val defaultBackend: Backend = TreadleBackend`
    */
   val defaultBackend: Backend = VerilatorBackend
 
@@ -84,6 +79,8 @@ object TesterDriver extends BackendCompilationUtilities {
         executeTreadle(t, additionalVResources, annotations, nameHint)
       case VerilatorBackend =>
         executeVerilog(t, additionalVResources, annotations, nameHint)
+      case NoBackend =>
+        true
       case _ =>
         throw new ChiselException(s"Unknown backend specified: $backendAnnotation")
     }
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index f61fa36a..cf8bd737 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.experimental._
 import chisel3.stage.ChiselStage
-import chisel3.testers.BasicTester
+import chisel3.testers.{TesterDriver, BasicTester}
 import chisel3.util._
 
 class BlackBoxInverter extends BlackBox {
diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala
index ffc10c88..93b9a036 100644
--- a/src/test/scala/chiselTests/BoringUtilsSpec.scala
+++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util.Counter
-import chisel3.testers.{BasicTester, TesterDriver}
+import chisel3.testers._
 import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform}
 import chisel3.util.experimental.BoringUtils
 
diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala
index 39cd65dc..be313546 100644
--- a/src/test/scala/chiselTests/ExtModule.scala
+++ b/src/test/scala/chiselTests/ExtModule.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.experimental._
 import chisel3.stage.ChiselStage
-import chisel3.testers.BasicTester
+import chisel3.testers.{BasicTester, TesterDriver}
 
 // Avoid collisions with regular BlackBox tests by putting ExtModule blackboxes
 // in their own scope.
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 8b7fddb0..0b9497b8 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util.Counter
-import chisel3.testers.BasicTester
+import chisel3.testers.{BasicTester, TesterDriver}
 import chisel3.stage.ChiselStage
 
 /** Multi-clock test of a Reg using a different clock via withClock */
diff --git a/src/test/scala/chiselTests/util/random/LFSRSpec.scala b/src/test/scala/chiselTests/util/random/LFSRSpec.scala
index 1dc2db41..90986637 100644
--- a/src/test/scala/chiselTests/util/random/LFSRSpec.scala
+++ b/src/test/scala/chiselTests/util/random/LFSRSpec.scala
@@ -6,8 +6,7 @@ import chisel3._
 import chisel3.stage.ChiselStage
 import chisel3.util.{Cat, Counter, Enum}
 import chisel3.util.random._
-import chisel3.testers.BasicTester
-
+import chisel3.testers.{BasicTester, TesterDriver}
 import chiselTests.{ChiselFlatSpec, Utils}
 
 import math.pow
@@ -109,12 +108,15 @@ class LFSRResetTester(gen: => LFSR, lockUpValue: BigInt) extends BasicTester {
 class LFSRSpec extends ChiselFlatSpec with Utils {
 
   def periodCheck(gen: (Int, Set[Int], LFSRReduce) => PRNG, reduction: LFSRReduce, range: Range): Unit = {
-    it should s"have a maximal period over a range of widths (${range.head} to ${range.last}) using ${reduction.getClass}" in {
+    val testName = s"have a maximal period over a range of widths (${range.head} to ${range.last})" +
+      s" using ${reduction.getClass}"
+    it should testName in {
       range
         .foreach{ width =>
           LFSR.tapsMaxPeriod(width).foreach{ taps =>
             info(s"""width $width okay using taps: ${taps.mkString(", ")}""")
-            assertTesterPasses(new LFSRMaxPeriod(PRNG(gen(width, taps, reduction))))
+            assertTesterPasses(new LFSRMaxPeriod(PRNG(gen(width, taps, reduction))),
+              annotations = TesterDriver.verilatorOnly)
           }
         }
     }