diff options
| author | Martin Schoeberl | 2019-01-25 23:24:01 -0800 |
|---|---|---|
| committer | Richard Lin | 2019-01-25 23:24:01 -0800 |
| commit | 5509cdd4c8332c53151e10ba5bdbe0684af1c05b (patch) | |
| tree | 15f4a7e8f83e0d249918bbce4198160fb2c5360f /src/test/scala/chiselTests/MultiClockSpec.scala | |
| parent | 4f5ec211cb59f9da37dbe91d0dfcb93c4d3d84c9 (diff) | |
WireDefault instead of WireInit, keep WireInit around (#986)
Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 88856009..6e84c9b2 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -54,7 +54,7 @@ class MultiClockSubModuleTest extends BasicTester { /** Test withReset changing the reset of a Reg */ class WithResetTest extends BasicTester { - val reset2 = WireInit(false.B) + val reset2 = WireDefault(false.B) val reg = withReset(reset2 || reset.asBool) { RegInit(0.U(8.W)) } reg := reg + 1.U |