WireDefault instead of WireInit, keep WireInit around (#986)

15 files changed, 46 insertions, 46 deletions

diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index d4769f41..c5e9ed02 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -118,7 +118,7 @@ class AnalogSpec extends ChiselFlatSpec {
   it should "NOT be connectable to UInts" in {
     a [Exception] should be thrownBy {
       runTester { new BasicTester {
-        val uint = WireInit(0.U(32.W))
+        val uint = WireDefault(0.U(32.W))
         val sint = Wire(Analog(32.W))
         sint := uint
       }}
diff --git a/src/test/scala/chiselTests/AutoClonetypeSpec.scala b/src/test/scala/chiselTests/AutoClonetypeSpec.scala
index 520fbdc4..cf88fd2e 100644
--- a/src/test/scala/chiselTests/AutoClonetypeSpec.scala
+++ b/src/test/scala/chiselTests/AutoClonetypeSpec.scala
@@ -156,7 +156,7 @@ class AutoClonetypeSpec extends ChiselFlatSpec {
   "Nested directioned anonymous Bundles" should "not need clonetype" in {
     elaborate { new Module {
       val io = IO(new NestedAnonymousBundle)
-      val a = WireInit(io)
+      val a = WireDefault(io)
       io.a.a := 1.U
     } }
   }
@@ -169,7 +169,7 @@ class AutoClonetypeSpec extends ChiselFlatSpec {
         }
       }
       val io = IO((new InnerClassThing).createBundle)
-      val a = WireInit(io)
+      val a = WireDefault(io)
     } }
   }
 }
diff --git a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
index 09cd687f..fc8eb73b 100644
--- a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
+++ b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala
@@ -66,8 +66,8 @@ class AutoNestedCloneSpec extends ChiselFlatSpec with Matchers {
     elaborate {
       class TestModule(w: Int) extends Module {
         val io = IO(new BundleWithAnonymousInner(w) )
-        val w0 = WireInit(io)
-        val w1 = WireInit(io.inner)
+        val w0 = WireDefault(io)
+        val w1 = WireDefault(io.inner)
       }
       new TestModule(8)
     }
@@ -82,8 +82,8 @@ class AutoNestedCloneSpec extends ChiselFlatSpec with Matchers {
         val io = IO(new Bundle {
           val inner = Input(bun)
         })
-        val w0 = WireInit(io)
-        val w1 = WireInit(io.inner)
+        val w0 = WireDefault(io)
+        val w1 = WireDefault(io.inner)
       }
       new TestModule(8)
     }
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
index 03abb7dc..d8fc70ac 100644
--- a/src/test/scala/chiselTests/BetterNamingTests.scala
+++ b/src/test/scala/chiselTests/BetterNamingTests.scala
@@ -26,12 +26,12 @@ class PerNameIndexing(count: Int) extends NamedModuleTester {
 // Note this only checks Iterable[Chisel.Data] which excludes Maps
 class IterableNaming extends NamedModuleTester {
   val seq = Seq.tabulate(3) { i =>
-    Seq.tabulate(2) { j => expectName(WireInit((i * j).U), s"seq_${i}_${j}") }
+    Seq.tabulate(2) { j => expectName(WireDefault((i * j).U), s"seq_${i}_${j}") }
   }
-  val optSet = Some(Set(expectName(WireInit(0.U), "optSet_0"),
-                        expectName(WireInit(1.U), "optSet_1"),
-                        expectName(WireInit(2.U), "optSet_2"),
-                        expectName(WireInit(3.U), "optSet_3")))
+  val optSet = Some(Set(expectName(WireDefault(0.U), "optSet_0"),
+                        expectName(WireDefault(1.U), "optSet_1"),
+                        expectName(WireDefault(2.U), "optSet_2"),
+                        expectName(WireDefault(3.U), "optSet_3")))
 
   val stack = mutable.Stack[Module]()
   for (i <- 0 until 4) {
@@ -83,7 +83,7 @@ class BetterNamingTests extends ChiselFlatSpec {
       if (withLits) {
         List(8.U, -3.S, 1.25.F(2.BP))
       }
-      WireInit(3.U)
+      WireDefault(3.U)
     }
     val withLits = chisel3.Driver.emit(() => new MyModule(true))
     val noLits = chisel3.Driver.emit(() => new MyModule(false))
diff --git a/src/test/scala/chiselTests/DontTouchSpec.scala b/src/test/scala/chiselTests/DontTouchSpec.scala
index 6759222c..f916b20a 100644
--- a/src/test/scala/chiselTests/DontTouchSpec.scala
+++ b/src/test/scala/chiselTests/DontTouchSpec.scala
@@ -27,7 +27,7 @@ class HasDeadCode(withDontTouch: Boolean) extends Module {
   val inst = Module(new HasDeadCodeChild(withDontTouch))
   inst.io.a := io.a
   io.b := inst.io.b
-  val dead = WireInit(io.a + 1.U)
+  val dead = WireDefault(io.a + 1.U)
   if (withDontTouch) {
     dontTouch(dead)
   }
diff --git a/src/test/scala/chiselTests/EnumSpec.scala b/src/test/scala/chiselTests/EnumSpec.scala
index e0069060..e0ec07f8 100644
--- a/src/test/scala/chiselTests/EnumSpec.scala
+++ b/src/test/scala/chiselTests/EnumSpec.scala
@@ -11,7 +11,7 @@ class EnumSpec extends ChiselFlatSpec {
   "1-entry Enums" should "work" in {
     assertTesterPasses(new BasicTester {
       val onlyState :: Nil = Enum(1)
-      val wire = WireInit(onlyState)
+      val wire = WireDefault(onlyState)
       chisel3.assert(wire === onlyState)
       stop()
     })
diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala
index 0e4cc3e7..3bedf87f 100644
--- a/src/test/scala/chiselTests/MixedVecSpec.scala
+++ b/src/test/scala/chiselTests/MixedVecSpec.scala
@@ -69,7 +69,7 @@ class MixedVecZeroEntryTester extends BasicTester {
     val io = IO(Output(bundleWithZeroEntryVec))
     io.foo := false.B
   })
-  WireInit(m.io.bar)
+  WireDefault(m.io.bar)
 
   stop()
 }
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 88856009..6e84c9b2 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -54,7 +54,7 @@ class MultiClockSubModuleTest extends BasicTester {
 
 /** Test withReset changing the reset of a Reg */
 class WithResetTest extends BasicTester {
-  val reset2 = WireInit(false.B)
+  val reset2 = WireDefault(false.B)
   val reg = withReset(reset2 || reset.asBool) { RegInit(0.U(8.W)) }
   reg := reg + 1.U
 
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index 6d74fbc0..6ae38a24 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -65,7 +65,7 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "generate proper printf for simple Decimal printing" in {
     class MyModule extends BasicTester {
-      val myWire = WireInit(1234.U)
+      val myWire = WireDefault(1234.U)
       printf(p"myWire = ${Decimal(myWire)}")
     }
     val firrtl = Driver.emit(() => new MyModule)
@@ -142,8 +142,8 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "print UInts and SInts as Decimal by default" in {
     class MyModule extends BasicTester {
-      val myUInt = WireInit(0.U)
-      val mySInt = WireInit(-1.S)
+      val myUInt = WireDefault(0.U)
+      val mySInt = WireDefault(-1.S)
       printf(p"$myUInt & $mySInt")
     }
     val firrtl = Driver.emit(() => new MyModule)
diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala
index 15ce943b..d38aa1e4 100644
--- a/src/test/scala/chiselTests/StrongEnum.scala
+++ b/src/test/scala/chiselTests/StrongEnum.scala
@@ -217,7 +217,7 @@ class InvalidEnumOpsTester extends BasicTester {
 
 class IsLitTester extends BasicTester {
   for (e <- EnumExample.all) {
-    val wire = WireInit(e)
+    val wire = WireDefault(e)
 
     assert(e.isLit())
     assert(!wire.isLit())
@@ -228,7 +228,7 @@ class IsLitTester extends BasicTester {
 class NextTester extends BasicTester {
   for ((e,n) <- EnumExample.all.zip(EnumExample.litValues.tail :+ EnumExample.litValues.head)) {
     assert(e.next.litValue == n.litValue)
-    val w = WireInit(e)
+    val w = WireDefault(e)
     assert(w.next === EnumExample(n))
   }
   stop()
@@ -238,7 +238,7 @@ class WidthTester extends BasicTester {
   assert(EnumExample.getWidth == EnumExample.litValues.last.getWidth)
   assert(EnumExample.all.forall(_.getWidth == EnumExample.litValues.last.getWidth))
   assert(EnumExample.all.forall{e =>
-    val w = WireInit(e)
+    val w = WireDefault(e)
     w.getWidth == EnumExample.litValues.last.getWidth
   })
   stop()
diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala
index 2cfe16d2..81cf690a 100644
--- a/src/test/scala/chiselTests/SwitchSpec.scala
+++ b/src/test/scala/chiselTests/SwitchSpec.scala
@@ -12,7 +12,7 @@ class SwitchSpec extends ChiselFlatSpec {
       elaborate(new Module {
         val io = IO(new Bundle {})
         val state = RegInit(0.U)
-        val wire = WireInit(0.U)
+        val wire = WireDefault(0.U)
         switch (state) {
           is (wire) { state := 1.U }
         }
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index f3cf3bca..a7137699 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -21,7 +21,7 @@ class FinishTester extends BasicTester {
     stop()
   }
 
-  val test_wire = WireInit(1.U(test_wire_width.W))
+  val test_wire = WireDefault(1.U(test_wire_width.W))
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index d8e3be10..d8fde208 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -149,7 +149,7 @@ class ZeroEntryVecTester extends BasicTester {
     val io = IO(Output(bundleWithZeroEntryVec))
     io.foo := false.B
   })
-  WireInit(m.io.bar)
+  WireDefault(m.io.bar)
 
   stop()
 }
diff --git a/src/test/scala/chiselTests/WidthSpec.scala b/src/test/scala/chiselTests/WidthSpec.scala
index 0011c532..4fcebb32 100644
--- a/src/test/scala/chiselTests/WidthSpec.scala
+++ b/src/test/scala/chiselTests/WidthSpec.scala
@@ -78,7 +78,7 @@ class RegWidthSpec extends WireRegWidthSpecImpl {
   def builder[T <: Data](x: T): T = Reg(x)
 }
 
-abstract class WireInitRegInitSpecImpl extends ChiselFlatSpec {
+abstract class WireDefaultRegInitSpecImpl extends ChiselFlatSpec {
   def name: String
   def builder1[T <: Data](x: T): T
   def builder2[T <: Data](x: T, y: T): T
@@ -101,7 +101,7 @@ abstract class WireInitRegInitSpecImpl extends ChiselFlatSpec {
 
   it should "NOT set width if passed a non-literal" in {
     assertInferredWidth(4) {
-      val w = WireInit(3.U(4.W))
+      val w = WireDefault(3.U(4.W))
       builder1(w)
     }
   }
@@ -133,54 +133,54 @@ abstract class WireInitRegInitSpecImpl extends ChiselFlatSpec {
 
   it should "set the width if the template type has a set width" in {
     assertKnownWidth(4) {
-      WireInit(UInt(4.W), 0.U)
+      WireDefault(UInt(4.W), 0.U)
     }
     assertKnownWidth(4) {
-      WireInit(UInt(4.W), 0.U(2.W))
+      WireDefault(UInt(4.W), 0.U(2.W))
     }
     assertKnownWidth(4) {
-      val w = WireInit(new SimpleBundle, SimpleBundle.intoWire())
+      val w = WireDefault(new SimpleBundle, SimpleBundle.intoWire())
       w.x
     }
     assertKnownWidth(4) {
       val x = Wire(Vec(1, UInt()))
       x(0) := 0.U(4.W)
-      val w = WireInit(Vec(1, UInt(4.W)), x)
+      val w = WireDefault(Vec(1, UInt(4.W)), x)
       w(0)
     }
   }
 
   it should "infer the width if the template type has no width" in {
     val templates = Seq(
-      () => 0.U, () => 0.U(2.W), () => WireInit(0.U), () => WireInit(0.U(2.W))
+      () => 0.U, () => 0.U(2.W), () => WireDefault(0.U), () => WireDefault(0.U(2.W))
     )
     for (gen <- templates) {
       assertInferredWidth(4) {
-        val w = WireInit(UInt(), gen())
+        val w = WireDefault(UInt(), gen())
         w := 0.U(4.W)
         w
       }
     }
     assertInferredWidth(4) {
-      val w = WireInit(new SimpleBundle, SimpleBundle.intoWire())
+      val w = WireDefault(new SimpleBundle, SimpleBundle.intoWire())
       w.y
     }
     assertInferredWidth(4) {
       val x = Wire(Vec(1, UInt()))
       x(0) := 0.U(4.W)
-      val w = WireInit(Vec(1, UInt()), x)
+      val w = WireDefault(Vec(1, UInt()), x)
       w(0)
     }
   }
 }
 
-class WireInitWidthSpec extends WireInitRegInitSpecImpl {
-  def name = "WireInit"
-  def builder1[T <: Data](x: T): T = WireInit(x)
-  def builder2[T <: Data](x: T, y: T): T = WireInit(x, y)
+class WireDefaultWidthSpec extends WireDefaultRegInitSpecImpl {
+  def name = "WireDefault"
+  def builder1[T <: Data](x: T): T = WireDefault(x)
+  def builder2[T <: Data](x: T, y: T): T = WireDefault(x, y)
 }
 
-class RegInitWidthSpec extends WireInitRegInitSpecImpl {
+class RegInitWidthSpec extends WireDefaultRegInitSpecImpl {
   def name = "RegInit"
   def builder1[T <: Data](x: T): T = RegInit(x)
   def builder2[T <: Data](x: T, y: T): T = RegInit(x, y)
diff --git a/src/test/scala/chiselTests/WireSpec.scala b/src/test/scala/chiselTests/WireSpec.scala
index 051880ee..7a1e1e06 100644
--- a/src/test/scala/chiselTests/WireSpec.scala
+++ b/src/test/scala/chiselTests/WireSpec.scala
@@ -5,16 +5,16 @@ package chiselTests
 import chisel3._
 
 class WireSpec extends ChiselFlatSpec {
-  "WireInit.apply" should "work" in {
-    assertCompiles("WireInit(UInt(4.W), 2.U)")
+  "WireDefault.apply" should "work" in {
+    assertCompiles("WireDefault(UInt(4.W), 2.U)")
   }
   it should "allow DontCare" in {
-    assertCompiles("WireInit(UInt(4.W), DontCare)")
+    assertCompiles("WireDefault(UInt(4.W), DontCare)")
   }
   it should "not allow DontCare to affect type inference" in {
-    assertCompiles("val x: UInt = WireInit(UInt(4.W), DontCare)")
+    assertCompiles("val x: UInt = WireDefault(UInt(4.W), DontCare)")
   }
   it should "not allow init argument to affect type inference" in {
-    assertDoesNotCompile("val x: UInt = WireInit(UInt(4.W), 2.S)")
+    assertDoesNotCompile("val x: UInt = WireDefault(UInt(4.W), 2.S)")
   }
 }