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Diffstat (limited to 'src/test/scala/chiselTests/AnalogSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/AnalogSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala index d4769f41..c5e9ed02 100644 --- a/src/test/scala/chiselTests/AnalogSpec.scala +++ b/src/test/scala/chiselTests/AnalogSpec.scala @@ -118,7 +118,7 @@ class AnalogSpec extends ChiselFlatSpec { it should "NOT be connectable to UInts" in { a [Exception] should be thrownBy { runTester { new BasicTester { - val uint = WireInit(0.U(32.W)) + val uint = WireDefault(0.U(32.W)) val sint = Wire(Analog(32.W)) sint := uint }} |