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Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 88856009..6e84c9b2 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -54,7 +54,7 @@ class MultiClockSubModuleTest extends BasicTester { /** Test withReset changing the reset of a Reg */ class WithResetTest extends BasicTester { - val reset2 = WireInit(false.B) + val reset2 = WireDefault(false.B) val reg = withReset(reset2 || reset.asBool) { RegInit(0.U(8.W)) } reg := reg + 1.U |